On 13/04/17 14:29, Julien Grall wrote:
Hi Julien,
>> The development of the ARM ITS emulation support has taken more time
>> than anticipated and I won't be able to address and fix all outstanding
>> comments until the official code freeze date.
>>
>> However the first part of the series is in a
Hi,
I wanted to run some ideas on how to prevent the race conditions we are
facing with the ITS emulation and removing devices and/or LPIs.
I think Stefano's idea of tagging a discarded LPI is the key, but still
some details are left to be solved.
I think we are dealing with two issues:
1) A guest
On 08/04/17 00:12, Julien Grall wrote:
>
>
> On 08/04/2017 00:06, André Przywara wrote:
>> On 07/04/17 23:59, Julien Grall wrote:
>>> Hi Andre,
>>>
>>> On 07/04/2017 18:32, Andre Przywara wrote:
>>>> When creating the device tree for a doma
On 07/04/17 23:59, Julien Grall wrote:
> Hi Andre,
>
> On 07/04/2017 18:32, Andre Przywara wrote:
>> When creating the device tree for a domain using an emulated GICv3,
>> we will later need to add the respective ITS subnodes as well.
>> Prepare a stub function to be later filled with the actual c
On 07/04/17 23:09, Stefano Stabellini wrote:
> On Fri, 7 Apr 2017, Stefano Stabellini wrote:
>> On Fri, 7 Apr 2017, Julien Grall wrote:
>>> Hi Andre,
>>>
>>> On 04/07/2017 09:46 PM, André Przywara wrote:
>>>> On 07/04/17 20:07, Stefano Stabellini
On 07/04/17 20:07, Stefano Stabellini wrote:
> On Fri, 7 Apr 2017, Andre Przywara wrote:
>> For LPIs the struct pending_irq's are somewhat dynamically allocated and
>> the pointers are stored in a radix tree. While I convinced myself that
>> an invalid LPI number can't make it into the core code, p
On 06/04/17 12:42, Julien Grall wrote:
> Hi,
>
> On 06/04/17 11:21, Andre Przywara wrote:
>> Hi,
>>
>> On 06/04/17 02:04, Stefano Stabellini wrote:
>>> On Thu, 6 Apr 2017, Andre Przywara wrote:
To let a guest know about the availability of virtual LPIs, set the
respective bits in the vir
On 06/04/17 23:19, Julien Grall wrote:
> Hi Andre,
>
> On 04/06/2017 12:18 AM, Andre Przywara wrote:
>> Each ITS maps a pair of a DeviceID (for instance derived from a PCI
>> b/d/f triplet) and an EventID (the MSI payload or interrupt ID) to a
>> pair of LPI number and collection ID, which points
On 06/04/17 22:43, Julien Grall wrote:
Salut Julien,
> On 04/06/2017 12:19 AM, Andre Przywara wrote:
>> Emulate the memory mapped ITS registers and provide a stub to introduce
>> the ITS command handling framework (but without actually emulating any
>> commands at this time).
>>
>> Signed-off-by:
On 04/04/17 17:51, Julien Grall wrote:
> Hi Andre,
>
> On 03/04/17 21:28, Andre Przywara wrote:
>> The INV command instructs the ITS to update the configuration data for
>> a given LPI by re-reading its entry from the property table.
>> We don't need to care so much about the priority value, but e
On 22/03/17 23:44, Stefano Stabellini wrote:
> On Thu, 16 Mar 2017, Andre Przywara wrote:
>> For the same reason that allocating a struct irq_desc for each
>> possible LPI is not an option, having a struct pending_irq for each LPI
>> is also not feasible. However we actually only need those when an
On 22/03/17 15:23, Julien Grall wrote:
> Hi Andre,
>
> On 16/03/17 11:20, Andre Przywara wrote:
>> Instead of directly manipulating the tables in memory, an ITS driver
>> sends commands via a ring buffer in normal system memory to the ITS h/w
>> to create or alter the LPI mappings.
>> Allocate mem
Hi,
On 22/03/17 13:52, Julien Grall wrote:
> Hi Andre,
>
> On 03/16/2017 11:20 AM, Andre Przywara wrote:
>> Each ITS maps a pair of a DeviceID (for instance derived from a PCI
>> b/d/f triplet) and an EventID (the MSI payload or interrupt ID) to a
>> pair of LPI number and collection ID, which po
On 21/03/17 22:57, Stefano Stabellini wrote:
> On Thu, 16 Mar 2017, Andre Przywara wrote:
>> The ARM GICv3 provides a new kind of interrupt called LPIs.
>> The pending bits and the configuration data (priority, enable bits) for
>> those LPIs are stored in tables in normal memory, which software has
On 13/01/17 19:37, Stefano Stabellini wrote:
> On Thu, 12 Jan 2017, Andre Przywara wrote:
Hi Stefano,
...
+list_for_each_entry(lpi_irq, &v->arch.vgic.pending_lpi_list, entry)
+{
+if ( lpi_irq->pirq.irq == lpi )
+return &lpi_irq->pirq;
+
+
On 13/04/16 16:55, Julien Grall wrote:
> The register HPFAR_EL2 (resp. HPFAR on arm32) contains the bits [47:12]
> (resp. [39:12]) of the faulting IPA. Unlike other registers that represent
> an address, the upper bits of the IPA are stored in the register bits
> [4:39] (resp. [4:21]).
>
> However
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