Regarding items 3) and 4):
3) Indeed, bhyve does not explicitly forbid writing to 0x3c. I meant the
following. The interrupt line is set is pci_emul.c in bhyve:
pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin));
Bhyve asserts interrupts with pci_irq_assert in amd64/pci_irq.c. We need
1) The problem with PIT. Can be solved as you proposed or by
patching Mezzano. The bhyve patch would be the best option for that: it's
useful for
other older o/s's (DOS).
2) Mezzano assumes that Intel AHCI controllers report no more than 6
ports. Can be solved by patching Mezzano or defining M
