Alex,Thank you very much for all these useful informations. Really appreciate
it.Cheers
Sent from Yahoo Mail for iPhone
On Sunday, July 12, 2020, 8:19 PM, Alex Williamson
wrote:
On Sun, Jul 12, 2020 at 6:36 PM Yv Lin wrote:
After more thoughts, I guess that 1) normally ppl don't enable v
On Sun, Jul 12, 2020 at 6:36 PM Yv Lin wrote:
> After more thoughts, I guess that
> 1) normally ppl don't enable vIOMMU unless they need to use a nested
> guest, as vIOMMU is slow and the memory accounting issue you just mentioned.
>
vIOMMU w/ device assignment is more often used for DPDK in a g
After more thoughts, I guess that
1) normally ppl don't enable vIOMMU unless they need to use a nested guest,
as vIOMMU is slow and the memory accounting issue you just mentioned.
2) host IOMMU driver actually can do io page fault and on-demanding
pinning/mapping for ATS/PRI-capable device, but cur
On Sun, Jul 12, 2020 at 6:16 PM Yv Lin wrote:
>
> Here are some summaries that I learned from what you told.
> 1) If a device is passed through to guestOS via vfio, and there is no
> IOMMU present in guestOS. all memory regions within the device address
> space will be pinned down. if IOMMU is pr
On Sun, Jul 12, 2020 at 4:57 PM Alex Williamson
wrote:
> On Sun, Jul 12, 2020 at 5:38 PM Yv Lin wrote:
>
>>
>>
>> On Sun, Jul 12, 2020 at 1:59 PM Alex Williamson <
>> alex.l.william...@gmail.com> wrote:
>>
>>> On Sun, Jul 12, 2020 at 12:25 PM Yv Lin wrote:
>>>
Btw, IOMMUv2 can support peri
On Sun, Jul 12, 2020 at 5:38 PM Yv Lin wrote:
>
>
> On Sun, Jul 12, 2020 at 1:59 PM Alex Williamson <
> alex.l.william...@gmail.com> wrote:
>
>> On Sun, Jul 12, 2020 at 12:25 PM Yv Lin wrote:
>>
>>> Btw, IOMMUv2 can support peripheral page request (PPR) so in theory if
>>> an end point pcie devi
On Sun, Jul 12, 2020 at 1:59 PM Alex Williamson
wrote:
> On Sun, Jul 12, 2020 at 12:25 PM Yv Lin wrote:
>
>> Btw, IOMMUv2 can support peripheral page request (PPR) so in theory if an
>> end point pcie device can support ATS/PRI, pinning down all memory is not
>> necessary, does current vfio driv
On Sun, Jul 12, 2020 at 12:25 PM Yv Lin wrote:
> Btw, IOMMUv2 can support peripheral page request (PPR) so in theory if an
> end point pcie device can support ATS/PRI, pinning down all memory is not
> necessary, does current vfio driver or qemu has corresponding support to
> save pinned memory?
>
Btw, IOMMUv2 can support peripheral page request (PPR) so in theory if an
end point pcie device can support ATS/PRI, pinning down all memory is not
necessary, does current vfio driver or qemu has corresponding support to
save pinned memory?
thanks.
On Sun, Jul 12, 2020 at 11:03 AM Yv Lin wrote:
Hi Alex,
thanks for the detailed explanation. it does clarify more to me. I read the
vfio_listener_region_add() more carefully. It seems check every
memory region against container's host window, for IOMMUv1 vfio device, the
host window is always 64bit full range （vfio_host_win_add(container, 0,
(h
vfio_dma_map() is the exclusive means that QEMU uses to insert translations
for an assigned device. It is not only used by AMD vIOMMU, in fact that's
probably one of the less tested use vectors, it's used when QEMU
establishes any sort of memory mapping for the VM. Any mapping that could
possibly
I'm new to qemu and vfio and looking for some information about if a pcie
device passed through to guestOS by vfio needs the hypervisor to pin down
all guest memory(all VM memory). I found the link
https://lkml.org/lkml/2018/10/30/221. it says "it shows the whole guest
memory were pinned (vfio_pin_
12 matches
Mail list logo
