Hi all,
I am using USRP B200mini/B205 to develop a custom DSP. For that purpose, I am
trying to find an insertion point in the Ettus FPGA code.
I started with modifying the code in b205.v by tying RX and TX to a constant
value and expecting to see the same value when running SDR. The code compi
r
On Sep 26, 2017 11:18 AM, Ezequiel Alfíe wrote:
Hi,
I ran into that issue once and I simply recompiled UHD with the relevant lines
commented out.
regards
On Mon, Sep 25, 2017 at 3:54 PM, Shoorveer Singh via USRP-users
mailto:usrp-users@lists.ettus.com>> wrote:
Hi all,
I am using US
ere is a path from host through FPGA to AD9364 and back to
the host, sounds like you severed that path, so the test words never make it
there and back.
-Trip
From: USRP-users [mailto:usrp-users-boun...@lists.ettus.com] On Behalf Of
Shoorveer Singh via USRP-users
Sent: Tuesday, Septem
Hi,
I am trying to modify the Ettus’s FPGA code and build the new code to get the
bit file. But it takes a very long time for every build to be done. I am using
Xilinx ISE for this work.
Is there any way I can get it to work faster?
--
Thanks and Regards
Shoor
s the build process is memory-intensive, but only up to a point.
For the B200/B210 FPGA, a system with 8 GB memory should suffice.
Xilinx ISE won't really take advantage of multiple cores, so using a CPU with
lots of cores won't help much.
--Neel Pandeya
On 13 October 2017 at 09:34
