Hello,
I'm very new to UHD and USRP stuff. I want to ask if it is possible to
integrate a converter with format unsupported by UHD, for example, s32 on
device (otw) and f32 on host (cpu)? Also, is there any explicit document
for how I can do this?
Sorry if my question is rather unclear because I'm
I mean s16 -> f32 not sc16 -> fc32, which is already implemented.
I looked through the document but it's not clear to me. I'm not sure about
UHD code structure. Could you explain in more details?
Sorry for any confusion.
___
USRP-users mailing list
USRP-
s16 (int16_t) -> f32 (float) is not implemented.
https://files.ettus.com/manual/structuhd_1_1stream__args__t.html
I also checked the converters in host/lib/convert/ and couldn't find it.
Am I missing something?
Also, when I create a new converter do I have to rebuild the UHD?
Thanks.
On Tue, Jan
Hello,
I have a small issue. I want to use the prebuilt fft block to check the
behavior of CORDIC block in a testbench. It returned an error:
ERROR: [VRFC 10-2063] Module not found while processing module
instance
[/home/kei/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/noc_block_fft.v:237]
Obviously axi_f
Hello,
I'm trying to build a polyphase filterbank block with RFNoC. First I had
looked if there already exists some work on it. I found this
https://github.com/EttusResearch/rfnoc-pfb-channelizer
but it doesn't seem to be developed yet. Also I've tested the current
noc_block_pfb on current uhd-fpg
are you seeing?
>
> Regards,
> - Nicolas
>
> On Tue, Feb 27, 2018 at 7:09 PM, Kei Nguyen via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Hello,
>>
>> I'm trying to build a polyphase filterbank block with RFNoC. First I had
>> loo
Hello, is this problem resolved? I am facing the same issue in the last
email. Also, I tried to receive the relay signal with another usrp but it
doesn't receive anything in my transmit frequency.
Hai
___
USRP-users mailing list
USRP-users@lists.ettus.co
ts the problem
>
> If you put effort into your question, we can put effort into answering you.
>
> Nick
>
> On Thu, Mar 8, 2018 at 10:39 AM Kei Nguyen via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Hello, is this problem res
409-gec9138eb and gnuradio version
>> 3.7.12git-295-ga0adcd33.
>> Sorry for the long post.
>>
>>
>>
>> On Fri, Mar 9, 2018 at 12:21 PM, Nick Foster
>> wrote:
>>
>>> You're going to have to ask a better question than that. Please provide
>>>
priately. I would guess that the lights are on because you have filled
>> up all fifos.
>>
>> Sam
>>
>>
>> On Mar 9, 2018, 10:39 AM -0800, Kei Nguyen via USRP-users , wrote:
>>
>> Thanks. After setting spp=600 and omit the DMA FIFO, it doesn't
Hello,
I'm testing the RFNoC block adder/subtractor to integrate the function in
my custom block. I use two flowgraph to test it in downstream and upstream
case:
1) Radio RX --> Split stream -->DDC x2 (one of them shifts the signal by 2
MHz) --> Adder/subtractor --> qt gui sink
2)Signal source 1
Hello,
i'm also working on the way to pass a series of values from the host to the
FPGA, although I don't use RFNoC and just work in the radio domain of
uhd-fpga's radio file. Is it possible to do that by just using a normal
setting_reg but not an axi-supported register?
Regards,
Kei
> Hey Jason
12 matches
Mail list logo