Hi,
Below is a question about sytemverilog support from August, that seems
unresolved.
I found this workaround, but why does the scripted flow not support
systemverilog design files?
Are there plans to make this change to support designs in sytemverilog?
If not, then can you please point m
I tried following these directions several times.
https://kb.ettus.com/Getting_Started_with_RFNoC_Development#Environment_Setup
First with manual build, then with pybombs. I always get an error at some
point.
My latest is with pybombs when I run this command.
pybombs --config makewidth=7 prefix
Hi Guys,
One thing that seems like an easy improvement to the USRP fpga build process
would be to check that all the source files are present prior to launching a 2
hour process.
If you are missing an RFNOC OOT module, then it isn't until after the build-ip
step is finished that you find out th
