[USRP-users] N210 + UBX Power Calibration

2021-09-07 Thread Ernest Fardin via USRP-users
Hi, I'm trying to calibrate the receive power on a USRP N210 with a UBX daughterboard. Using UHD 4.0, I can get uhd_power_cal.py to run by adding an N210Calibrator class to usrp_calibrator.py. N210Calibrator overloads the USRPCalibratorBase class. class N210Calibrator(USRPCalibratorBase): """

[USRP-users] Re: N210 + UBX Power Calibration

2021-09-08 Thread Ernest Fardin via USRP-users
Hi, Following up on this, the question I'm trying to answer is: "Can I calibrate the rx power on an N210 + UBX platform?" With the N210, has_rx_power_reference() returns False. Can I conclude f

[USRP-users] Re: N210 + UBX Power Calibration

2021-09-08 Thread Ernest Fardin via USRP-users
the N210 in order to apply the calibration data? [2] In order to get the reference power API to work on the N210, would that require changes to the N210 firmware, or just UHD? Regards, Ernest On Thu, Sep 9, 2021 at 7:34 AM Marcus D. Leech wrote: > On 2021-09-08 5:27 p.m., Ernest Fardin via U

[USRP-users] Re: N210 + UBX Power Calibration

2021-09-09 Thread Ernest Fardin via USRP-users
only very limited device coverage--for > example, I can't > really determine if it understands the concept of pluggable > daughtercards, so that the total index is composed of both the motherboard > AND daughtercard > serial numbers. Because, without that, any calibration

[USRP-users] X310 Daisy Chain

2022-07-17 Thread Ernest Fardin via USRP-users
Hi, Am I able to daisy chain two X310s using the second 10 Gigabit Ethernet port with a 10 Gigabit Ethernet cable ? This would remove the requirement for an Ethernet switch. Thanks! Ernest ___ USRP-users m

[USRP-users] Re: x310 FW error

2023-03-06 Thread Ernest Fardin via USRP-users
Hi Maurizio, Compatibility number 33 indicates a fairly old version of the FPGA image, so it would be best to perform an update. To do this, run the command "/lib/bin/uhd_image_loader" --args="type=x300,addr=192.168.10.2" as per the error message, then cycle the power after updating the FPGA. Ch