I had noticed that the first ten samples of my application were always
coming up as zero regardless of whether it was 8-bits on host or 16-bits on
host. I went down the path of trying to reproduce a minimal example to
share with this mailing list, however I then realized that even the example
"rx_t
ading them into the software that consumes them.
On Thu, Nov 7, 2024 at 3:03 PM Marcus D. Leech
wrote:
> On 07/11/2024 14:53, Chris Wozny wrote:
> > I had noticed that the first ten samples of my application were always
> > coming up as zero regardless of whether it was 8-bits on
Marcus,
I was specifying SC16 on host and SC12 over-the-wire via:
uhd::stream_args_t stream_args("sc16","sc12"); // 16-bit integers on host,
12-bit over-the-wire
- Chris
On Mon, Aug 15, 2022 at 10:25 AM Marcus D. Leech
wrote:
> On 2022-08-14 20:57, Nikos Balkanas wrote:
> > Aaaah, it's the dr
Thank you all!
Question about the 4.3.0.0 FPGA builds using Vivado 2021.1: would you
expect the bitstreams for the b2xx to still be identical as previous
releases? Not sure if it’s anywhere as drastic as software compiler updates
where you’ll see a dramatic amount of changes in the binary.
Thanks
