Hi,
for quite a time (with breaks) am working on RFNoC Blocks based on Xilinx
System Generator. The only feasable way to integrate the System Generator
model into a RFNoC block, I found, was making a design checkpoint
(.dcp-file) out of it and importing it into Vivado. Integrating all the
verilog
Hi all,
I have rebuild my poly-phase channelizer block based on the the current uhd
version.
Find it on https://github.com/e33b1711/rfnoc-ppchan.
It is a RFNoC OOT-Module. Simulation, building and installation like
described in the RFNoC Getting Started Guide.
Feel free to use it and to write m
