Thanks David, that is helpful. I suspect that this tool lock bug shows up
more frequently when Vivado is struggling to meet timing. If you fix that
timing issue then the problem might become less frequent. It looks like
that path is on a reset going to a "synchronizer_false_path", which should
be a
Thank you for your answer,
I’m following your directions and I’m creating the yaml file with the relevant
elements in it, however since it is the first time that I create such a file
I’m facing some difficulties:
\-The 4 port DUC will need 4 new endpoints right?
\-all the addsub blocks that ar
Thank you! These commands all showed that I was indeed running version 4.8
now. I hadn’t realized that I needed to re-flash the FPGA after a file system
update. Once I did that, the QSFP connectivity returned, and all is well
again. Thank you again for your help! It is much appreciated. I
Wade and Sam,
The repeat FPGA build script was very useful. I was able to let it run and
find a build solution. That will let me proceed with my project, but I
still want to nail down why this showed up.
Some additional info: my design does not meet timing constraints, but it
still builds the bit
One more thing. I would start as small as possible. Just add one addsub
block and one null src sink and see if you can get it working with 2 tx
streams.
On Fri, Mar 14, 2025 at 10:06 AM Rob Kossler wrote:
>
> On Fri, Mar 14, 2025 at 5:57 AM wrote:
>
>> Thank you for your answer,
>>
>> I’m foll
** apologies for cross-posting **
Call for Contributions: SDRA-2025 Online and Friedrichshafen
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