And you can have an example in which to the standard firmware cutters
for example FFT and a window. And what is the sequence of actions when
downloading the firmware to the board?
вт, 3 авг. 2021 г. в 03:12, :
> I followed the guide here and was able to build a few simple images:
> https://kb.et
Hi Vladica & the USRP community - For those of you who have White Rabbit
equipment, you can download brand new hot off the buildbots WR FPGA images
(WX and XQ) for your N3x0 or N32x here <
https://drive.google.com/drive/folders/1y-AJA2ZBaHgwyRCiOfatfAyLSX0t1G7l?usp=sharing>
. Note that these are fo
I could really use some help guys.
i'm using an X310
i've added the siggen block to my HA FPGA image.
I've added the 'Loopback Patch' to gr-ettus which exposes skip property
propagation (but it's currently set to False as is default)
I made a custom gnuradio block using rfnocmodtool that accesses
Hi Michael,
Thanks for informing us about this. I would be happy to test it. I am in
the moment on vacation, but next week I will find some time to test it.
Best regards,
Vladica
On 03.08.21 17:17, Michael Dickens wrote:
Hi Vladica & the USRP community - For those of you who have White
Rabb
On 08/03/2021 11:08 AM, Marcin Wachowiak wrote:
Hello,
The signals provided at the input have quite low power, far below the
threshold of -20dbm. ( I don't know the exact values but I
additionally even added a 30dB attenuator for safety)
What I also found out is that the distortions are depende
Hello,
Thank You for the interest in my problem.
Yes I am feeding the signal into both RX2 ports. I have just repeated the same
thing symmetrically for TX/RX ports and the distortion was present again.
Kind regard,
Marcin Wachowiak
-Wiadomość oryginalna-
Od: usrp-users-requ...@lists.ett
Marcin, we are using the B210 in an application that requires a high degree of
coherency between the two Rx inputs. We rarely change the data capture from
20MSPS, unlike your case, but I have completed analysis of 260 1-Gb data files
and have not seen anything like what I saw in your videos. Whe
On 08/03/2021 12:20 PM, marcin.r.wachow...@gmail.com wrote:
Hello,
Thank You for the interest in my problem.
Yes I am feeding the signal into both RX2 ports. I have just repeated the same
thing symmetrically for TX/RX ports and the distortion was present again.
Kind regard,
Marcin Wachowiak
Wh
Thanks for the hint, reducing the files to only librte_pmd_* and
librte_mempool_* changed the error message.
Now what I get is:
VFIO gorup is not viable!
next to the 2 ports I wanted to use for the dpdk operations.
Digging a little bit sounded like the whole NIC had to be configured with the
Hello,
Power consumption is low until processing is started for the first time after
FPGA firmware loaded.
>From this point power consumption remains the same even if processing is
>stopped.
Power cycle will reduce power consumption but result in requiring to load FPGA
firmware which is length
My gut tells me this would require exotic power management support in the FPGA
fabric itself. Which it doesn’t as far as I know, have.
Sent from my iPhone
> On Aug 3, 2021, at 6:44 PM, Ernest Poletaev wrote:
>
>
> Hello,
>
> Power consumption is low until processing is started for the firs
Thanks Marcus,
I was looking into it, there is power management in Spartan-6 FPGA (which I
suppose is the main power hog).
However, it requires using Suspend pin which is inaccessible on board due to
BGA package.
If we had PCB design we could modify wiring on FPGA to allow us to use this
pin,
My guess making this actually work would not be that simple.
PCB design files are proprietary to Ettus/NI.
Sent from my iPhone
> On Aug 3, 2021, at 7:39 PM, Ernest Poletaev wrote:
>
>
> Thanks Marcus,
>
> I was looking into it, there is power management in Spartan-6 FPGA (which I
> suppo
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