Hello,
We are planning on using an octoclock with several devices, including an N320.
The octoclock outputs a 5V 1pps signal, but I'm confused about the N320 1pps
input.
According to (https://kb.ettus.com/N320/N321):
"PPS - Pulse Per Second Using a PPS signal for timestamp synchronization
requ
Hello Jim,
hm, that knowledge base article must be wrong: The octoclock internally only
has a 3.3V
supply. But before I say something wrong here, let me check back.
Best regards,
Marcus
On 11.06.21 14:17, Jim Palladino wrote:
> Hello,
>
> We are planning on using an octoclock with several
On 06/11/2021 09:11 AM, Marcus Müller wrote:
Hello Jim,
hm, that knowledge base article must be wrong: The octoclock internally only
has a 3.3V
supply. But before I say something wrong here, let me check back.
Best regards,
Marcus
The 1PPS outputs on the Octoclock are bufered by 7404 invert
Hi Marcus,
Right -- the output of the Octoclock is 5V. I'm not seeing how the N320 can
accept that as an input. The knowledge base article says the N320 expects 5Vpp
at the 1pps input. But the schematics/parts data sheet for the input buffer
don't seem to support that . . . unless I'm missing s
Ah wait, you're right! I overlooked U120. I was actually also confused by
C200…C207, which
happen to be on VCC3V3 and would in numbers make sense to decouple the two
7404s, U204 and
U203. Sorry!
On 11.06.21 15:39, Marcus D. Leech wrote:
> On 06/11/2021 09:11 AM, Marcus Müller wrote:
>> Hello Ji
On 06/11/2021 09:45 AM, Jim Palladino wrote:
Hi Marcus,
Right -- the output of the Octoclock is 5V. I'm not seeing how the
N320 can accept that as an input. The knowledge base article says the
N320 expects 5Vpp at the 1pps input. But the schematics/parts data
sheet for the input buffer don't
On 18/05/2021 12:04, Margaux Bougeard wrote:
I am using the USRP E312 with UHD 4.0.0.0.
mpm_sw_version : 4.0.0.0-g90ce6062
product: e310_sg3
MPM Version: 3.0
FPGA Version: 6.0
Normally I should have access to MPM but I don't. If I add the lines
concerning MPM in the multi_usrp.py file, then I h
On 18/05/2021 18:33, Martin Braun wrote:
Hey Devin,
you don't need a calibrated receiver for a calibrated TX. I'll need to
get back to my setup to see if maybe there is a bug here and I simply
missed it because I had a lingering RX calibration file.
Devin,
sorry for the eternity between re
The schematic shows 33 Ohm series resistors on the logic-outputs. That's
probably dimensioned to get about 50 Ohm output impedance.
Last I tried an octoclock, driving a 50 Ohm load gives about a 2.5 V
amplitude pulse. This is from 2016-09, but maybe the schematic hasn't
changed since that.
[image:
On 04/06/2021 21:19, Rich Gopstein wrote:
I've successfully replaced the non-idle FPGA image on my UHD 4.0 E310
using uhd_image_loader.
What's the process to replace the idle FPGA image? I didn't see any
documentation on using uhd_image_loader for that.
I saw FPGA images in /user/share/uhd/
Hi Jim,
The congregation of Marcuses checked with R&D, and we figured out that in fact,
the
NC7SV157 in U24 was replaced by a SN74LVC2G34, which is OK up to 6.5 V input,
in Hardware
revisions starting with Rev C.
So, if (and only if) you have a N320 in a revision that's C or greater, you're
sa
Thanks. I'll give that a try.
Rich
On Fri, Jun 11, 2021 at 10:32 AM Martin Braun
wrote:
> On 04/06/2021 21:19, Rich Gopstein wrote:
> > I've successfully replaced the non-idle FPGA image on my UHD 4.0 E310
> > using uhd_image_loader.
> >
> > What's the process to replace the idle FPGA image?
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