Hello,
I have a working single-channel rfnoc fpga design file for the e310.
I am using the axi wrapper with simple mode enabled. Using the UHD
xml files instead of c++. 2 settings registers. Got it setup using
GNURadio. For a while I was running my flowgraph as 2 single stream
blocks (also buil
I have been struggling all day with why I can't build my OOT rfnoc blocks
for the N310 using v3.15.0.0. It appears that the problem is that there is
a file top/n3xx/Makefile.srcs that is clearing the RFNOC_OOT_SRCS variable
after it is set in the users OOT makefile. I just commented the line in
to
I had the same issues! I just ended up putting my verilog file paths in
Makefile.n3xx.inc and it works. This might need to be fixed unless I did
something wrong.
On Wed, Jan 29, 2020 at 16:18 Rob Kossler via USRP-users <
usrp-users@lists.ettus.com> wrote:
> I have been struggling all day with why
