[USRP-users] IOError: x300 fw poke32 - reply timed out

Hi, We are in the process of prototyping a setup using an X300 with two UBX-40 daughterboards to be used in the validation of an externally provided signal source. The daughterboards are each dedicated to one of two tasks: transmitting a pre-recorded reference signal in a loop at 50 MSps, and

Re: [USRP-users] IOError: x300 fw poke32 - reply timed out

Hi Stefan, I know it's not of great comfort when an engineer finds a problem to be /interesting/, but yours certainly is. So, first things first: if the computational power and memory of the host that your USRP is connected to allows, it might be good to have a packet capture in some kind of a rin

Re: [USRP-users] USRP E313 | WBFM Issues

Hi Ryan, hm, there's honestly quite a few things that can simply go wrong on a demodulation/DSP/signal side of things without nothing misbehaving or you doing any mistakes. Your single-tone test hence was very clever to do! So, my recommendation is this: First of all, verify that the reception st

[USRP-users] How to transmit different signals simultaneously?

Hi, I write to ask some questions about USRP X310. I use two SBX daughter boards, but I do not know how to control them separately. For example, how to let them transmit different signals simultaneously? Is there any published project that I can learn from? Best regard! Ge -- Ge Wang Ph.D Cand

Re: [USRP-users] How to transmit different signals simultaneously?

Hi Ge, so, the UHD API lets you define streamers with multiple channels. Then it's just a matter of calling send() with a list of multiple buffers to be sent. But: if you're new to all this, or want to use GNU Radio anyways, or rather build DSP than writing driver interfacing C++ code: GNU Radio'

Re: [USRP-users] PCIe driver frame size

Hi Eugene, I'm not an expert on the PCIe transport, but as far as I can tell from 3.11.0.1's uhd::transport::muxed_zero_copy_if::sptr make_muxed_pcie_msg_xport the PCIe frame sizes seem to be immutable (4 kB, in fact, which, subtracting header and dividing by sample bitwidth, leads to 1020 sampl

[USRP-users] general RFNoC timing question

I have a flowgraph I am running on an E310 using all stock RFNoC blocks. It looks a lot like this: RFNoC:Radio ---> RFNoC: Split Stream ---> RFNoC: FFT ---> RFNoC: Keep 1 in N ---> RFNoC: Log Power > GR: complex to float ---> GR:Raster Sink

[USRP-users] DMA FIFO Resizing

I noticed that the dma_fifo_block_ctrl.hpp file isn't included in the installation of UHD as of current master: https://github.com/EttusResearch/uhd/blob/6af6ac32c30d2dc0efa6eab61e4a3920649e3e62/host/include/uhd/rfnoc/CMakeLists.txt It seems like this is just a simple oversight, so I modified it

Re: [USRP-users] PCIe driver frame size

Yep, that's what seems to be the case. The whole point of PCIe is lower latency -- with a frame size that large I can get lower latency w/ 10 GbE and 500B frame size. I can't imagine it is a large effort to get that fixed :) ___ Eugene Grayver, Ph.D. Aerospace Corp., Princ

Re: [USRP-users] IOError: x300 fw poke32 - reply timed out

Hi Stefan, so I've talked to our main software sustainance hero, and we rather quickly came to the conclusion that it's pretty likely you should move on to the head of the 3.13 branch (remotes/origin/UHD-3.13). Are you building from source, or are you using binary packages? Best regards, Marcus

Re: [USRP-users] PCIe driver frame size

Well, there *is* a bit of history on these package sizes. Now, having had frequent communication with you: 4kB is an effect of system page sizes. For more detail, see x300_impl.hpp's comments on X300_PCIE_RX_DATA_FRAME_SIZE. But: you're right, this is a communicated transport property, but since yo

Re: [USRP-users] DMA FIFO Resizing

Hi Brian, thanks! Quick update first: raised the CMakeLists omission internally, should be fixed soon, far as I can tell. Best regards, Marcus On Mon, 2018-09-24 at 14:52 -0400, Brian Padalino via USRP-users wrote: > I noticed that the dma_fifo_block_ctrl.hpp file isn't included in the > installa

Re: [USRP-users] DMA FIFO Resizing

Hello Brian, so, the power-of-two FIFO sizes pretty much happen because you can only divide addresses by full bit prefixes. That seems to be reflected in noc_shell.v; not quite sure how deep the changes would have to go to get rid of that restriction. Best regards, Marcus On Mon, 2018-09-24 at 1

[USRP-users] Can't find a block controller for key FFT, using default block controller!

Re-pining this question > On Sep 2, 2018, at 10:48 PM, Rich Maes wrote: > > I am running a cross-compiled UHD environment on a E310. I have a couple > warning that appear when I am running my uhd_usrp_probe with a custom FPGA > image. The image I have created has 2 FFT’s and 2 Windows in

Re: [USRP-users] DMA FIFO Resizing

Hey Marcus, On Mon, Sep 24, 2018 at 5:22 PM Marcus Müller wrote: > Hello Brian, > > so, the power-of-two FIFO sizes pretty much happen because you can only > divide addresses by full bit prefixes. That seems to be reflected in > noc_shell.v; not quite sure how deep the changes would have to go t

Re: [USRP-users] Can't find a block controller for key FFT, using default block controller!

Hi Rich, This all looks OK to me. 1) the block controller warning just indicates there's no *custom* block controller for a particular block. By default the XML noc block definition will typically populate read/write registers in a default block controller just fine. 2) the errors at the end are

Re: [USRP-users] DMA FIFO Resizing

On 09/24/2018 02:52 PM, Brian Padalino via USRP-users wrote: I noticed that the dma_fifo_block_ctrl.hpp file isn't included in the installation of UHD as of current master: https://github.com/EttusResearch/uhd/blob/6af6ac32c30d2dc0efa6eab61e4a3920649e3e62/host/include/uhd/rfnoc/CMakeLists.txt