Re: [USRP-users] RFNoC FPGA OOT Xilinx IP Addition

2018-02-27 Thread EJ Kreinar via USRP-users
Hi Brian, There's a supported method to include OOT repos that can build and include xilinx IP (or basically any other IP that you need, including HLS. I've yet to try it with sysgen blocks, but that would probably work too). Basically you can use uhd_image_builder.py or uhd_image_builder_gui.py t

[USRP-users] set_rx_lo_source

2018-02-27 Thread Андрей 1 via USRP-users
Hello In the previous post(twinrx_freq_hopping example), I wrote that I could not get time in 5 ms for example twinrx_freq_hopping.I measure the commands execute time in the recieve loop and found with surprise that the set_rx_lo_source function for the first time worked 0 ms and the next time mor

[USRP-users] RFNoC polyphase filterbank

2018-02-27 Thread Kei Nguyen via USRP-users
Hello, I'm trying to build a polyphase filterbank block with RFNoC. First I had looked if there already exists some work on it. I found this https://github.com/EttusResearch/rfnoc-pfb-channelizer but it doesn't seem to be developed yet. Also I've tested the current noc_block_pfb on current uhd-fpg

Re: [USRP-users] RFNoC FPGA OOT Xilinx IP Addition

2018-02-27 Thread Brian Padalino via USRP-users
Hey EJ, On Tue, Feb 27, 2018 at 6:27 AM, EJ Kreinar wrote: > Hi Brian, > > There's a supported method to include OOT repos that can build and include > xilinx IP (or basically any other IP that you need, including HLS. I've yet > to try it with sysgen blocks, but that would probably work too). B

Re: [USRP-users] RFNoC polyphase filterbank

2018-02-27 Thread Nicolas Cuervo via USRP-users
Hello Kei, your email served as a reminder for the pending merge that contains a documentation update as well as some fixes on the channelizer, so I recommend you pull the latest changes before continuing using it. If that doesn't solve the issues that you are seeing, could you please elaborate o

Re: [USRP-users] RFNoC polyphase filterbank

2018-02-27 Thread Kei Nguyen via USRP-users
Hi Nicolas, I tried to create a new block mimicking the current pfb built in fpga-src with noc_block_pfb.v, pfb.v and pfb_stage.v. I did a simple testbench but got data out x... As I took a glance to the block, it seems weird to me that it doesn't use some fft filtering, or I'm misunderstandin

Re: [USRP-users] RFNoC FPGA OOT Xilinx IP Addition

2018-02-27 Thread EJ Kreinar via USRP-users
Sure, glad to help! Most of magic variables come from the Makefile workflow in uhd-fpga (suggest doing some greps in both uhd-fpga/usrp3/tools/make and uhd-fpga/usrp3/top). The OOT_DIR is a magic variable that's passed to the OOT directory, and it lets the Makefiles resolve relative pathing issue