Re: [USRP-users] using uhd_fft with usrp N210

2017-11-28 Thread Kyeong Su Shin via USRP-users
Dear Sung Bok,Lee: You are using BasicRX/BasicTX daughterboards. These daughterboards do not have any mixers, so they cannot 'tune' to any frequencies and you have to supply your own RF frontends to get reasonable performances. All these daughterboards do for you is just buffering the ADC/DAC and

Re: [USRP-users] using uhd_fft with usrp N210

2017-11-28 Thread Kyeong Su Shin via USRP-users
Dear Sung Bok,Lee: Forgot to mention - so, in short, all it can do is 'digitally' shifting signals if you use BasicRX/BasicTX daughterboards. The analog frontends do not filter any signals (although the daughterboards themselves act as poor low pass filters with bandwidth of 250MHz), nor mix them

[USRP-users] issue with RFNoC signal generator block on X310 (TLDR)

2017-11-28 Thread Dario Pennisi via USRP-users
Hi, A short question for which there is a larger underlying issue: if I connect a RX RFNoC Radio block to a TX RFNoC radio block, regardless of the presence of FIFOs in the middle nothing gets transmitted. The only way it works seems to be by passing through the host by inserting two fifos and s

Re: [USRP-users] Fwd: Re: USRP's B210 sluggish start of transmission

2017-11-28 Thread Piotr Krysik via USRP-users
W dniu 13.11.2017 o 11:36, Piotr Krysik via USRP-users pisze: > Dear list, > > Little update on transmitting bursts and simultaneous receiving with > USRP B210. When I connect anything that has some path between TX/RX SMA > port's body and inner female sleeve contact (like 3dB attenuator or even >

Re: [USRP-users] Ethernet over SFP+ in custom FPGA design (X3x0)

2017-11-28 Thread Christian Lenz via USRP-users
Ian and Sugandha, thank you very much for your comments and also for the attached file. Sadly, another three questions remain for the moment: 1. In the attached file, there is a series of 48? bits named "Ettus Padding". Is this an Ettus specific bit sequence and where can I find information o

[USRP-users] RFNoC OOT Module Error with FPGA Image

2017-11-28 Thread Avila, Jose A via USRP-users
Hello we are getting the following error when probing the FPGA in X310 after installing the created bit file. Error:Runtime error: Cannot get() on an uninitialized (empty) property. The testbench runs successfully but after creating the bit file and uploading it into the SDR we get the error

[USRP-users] B210 simultaneous Tx and Rx at 32 MS/s

2017-11-28 Thread Joan Olmos via USRP-users
Hi, I'm trying to transmit and receive simultaneously using B210 in single channel mode. The sampling rate for both Tx and Rx is 32 Msamples/s. I have a recent desktop computer with USB 3 running Debian. The UHD version is 3.9 LTS. The Tx streamer is started first and then the Rx streamer (bo

Re: [USRP-users] B210 simultaneous Tx and Rx at 32 MS/s

2017-11-28 Thread Marcus D. Leech via USRP-users
On 11/28/2017 06:11 PM, Joan Olmos via USRP-users wrote: Hi, I'm trying to transmit and receive simultaneously using B210 in single channel mode. The sampling rate for both Tx and Rx is 32 Msamples/s. I have a recent desktop computer with USB 3 running Debian. The UHD version is 3.9 LTS. The

Re: [USRP-users] Ethernet over SFP+ in custom FPGA design (X3x0)

2017-11-28 Thread Sugandha Gupta via USRP-users
I can answer the question related to the padding. I am not sure about the rest. Ettus Padding: An ethernet frame has 6 bytes of destination MAC address and 6 bytes of Source MAC address. Since we use 64 bits/8 bytes of data in one clock cycle, we add a 6 byte padding in front of the ethernet packe

[USRP-users] Linux Kernel Modules for X-Series PCIe Connectivity

2017-11-28 Thread john liu via USRP-users
Hi all, >From the manual http://files.ettus.com/manual/page_ni_rio_kernel.html ,we know *Currently, the latest supported kernel version is 4.2.x. * But the kernel version of ubnutu16.04 is newer than 4.2.x.So we have a plan to update this? thank you. best regards John

Re: [USRP-users] Ethernet over SFP+ in custom FPGA design (X3x0)

2017-11-28 Thread Ian Buckley via USRP-users
Christian, If memory serves me correctly the missing pages are due to that portion of the design using a proprietary NI ASIC that handles the PCIe interface and the flash storage of the FPGA config data. Since it handles config it would be reasonable to assume that circuit also supplies initial