Re: [USRP-users] TwinRX tuning timing

2017-07-16 Thread Jacob Gilbert via USRP-users
; The control-plane an data-plane run asynchronously to one another. The >> only guarantee is that samples that arrive after the tag will be after the >> comman has been issued. >> >> >> *From:* mle...@ripnet.com [mailto:mle...@ripnet.com ] >> *Sent:* Friday, July

Re: [USRP-users] TwinRX tuning timing

2017-07-15 Thread Marcus D. Leech via USRP-users
at arrive after the tag will be after the comman has been issued. *From:*mle...@ripnet.com <mailto:mle...@ripnet.com> [mailto:mle...@ripnet.com] *Sent:* Friday, July 14, 2017 12:34 PM *To:* Eugene Grayver <mailto:eugene.gray...@aero.org> *Cc:* usrp-us

Re: [USRP-users] TwinRX tuning timing

2017-07-15 Thread Jacob Gilbert via USRP-users
e after the > comman has been issued. > > > *From:* mle...@ripnet.com [mailto:mle...@ripnet.com ] > *Sent:* Friday, July 14, 2017 12:34 PM > *To:* Eugene Grayver > *Cc:* usrp-users@lists.ettus.com > *Subject:* Re: [USRP-users] TwinRX tuning timing > > > > The frequ

Re: [USRP-users] TwinRX tuning timing

2017-07-14 Thread Marcus D. Leech via USRP-users
:* Re: [USRP-users] TwinRX tuning timing The frequency tag is inserted at some point shortly after the command-set is issued to the hardware. There's no way for the various bits and pieces to tell when the underlying (mostly analog) hardware has converged to an "acceptable" steady-

Re: [USRP-users] TwinRX tuning timing

2017-07-14 Thread Eugene Grayver via USRP-users
PM To: Eugene Grayver Cc: usrp-users@lists.ettus.com Subject: Re: [USRP-users] TwinRX tuning timing The frequency tag is inserted at some point shortly after the command-set is issued to the hardware. There's no way for the various bits and pieces to tell when the underlying (mostly a

Re: [USRP-users] TwinRX tuning timing

2017-07-14 Thread Marcus D. Leech via USRP-users
The frequency tag is inserted at some point shortly after the command-set is issued to the hardware. There's no way for the various bits and pieces to tell when the underlying (mostly analog) hardware has converged to an "acceptable" steady-state operating mode. PLL synthesizers don't instantly s