ber 11, 2019 11:34 AM
> *To:* Quadri,Adnan ;
> usrp-users@lists.ettus.com
> *Subject:* Re: [USRP-users] RFNoC SVD Block
>
> Thanks! I'm always curious about how our hard- and software
> infrastructure is being used!
>
> By the way, in case you want to test a verilog SV
:34 AM
To: Quadri,Adnan ; usrp-users@lists.ettus.com
Subject: Re: [USRP-users] RFNoC SVD Block
Thanks! I'm always curious about how our hard- and software
infrastructure is being used!
By the way, in case you want to test a verilog SVD implementation
within a signal processing framework: Bow
ions or
> any significant findings.
>
> Thank you,
> Adnan
> From: Marcus Müller
> Sent: Friday, September 6, 2019 4:00 PM
> To: Quadri,Adnan ;
> usrp-users@lists.ettus.com
> Subject: Re: [USRP-users] RFNoC SVD Block
>
> Hello Adnan,
>
> I'm cu
findings.
Thank you,
Adnan
From: Marcus Müller
Sent: Friday, September 6, 2019 4:00 PM
To: Quadri,Adnan ; usrp-users@lists.ettus.com
Subject: Re: [USRP-users] RFNoC SVD Block
Hello Adnan,
I'm currently not aware of anyone doing that.
However, since one o
Hello Adnan,
I'm currently not aware of anyone doing that.
However, since one of the typical applications of beefier FPGAs is math
accelerators for linear algebra problems, it's more than likely someone
did in fact implement an SVD before, and you might just need to connect
it to a nocshell to ma
