Thanks Marcus!
Looking at the code, I have seen that the daughter board clock
rate can be change by including "dboard_clock_rate=10e6" in the
device arguments. If there is no phase synchronization issue, this
would be the best solution for me.
ISee also the UBX documentaion:
https://kb.ettus.com/U
Good description!
If you look into uhd/host/lib/usrp/dboard/dboard_ubx.cpp (I think), you
should find that the constructor looks through all the rates the
motherboard (X310 in your case) has to offer and picks the highest one
that works with your UBX. That'd be 25 MHz for the 0. revision of the
UBX
Hi Fabian
Thank you for your answer.
I have check the schematics of the X310. The reference clocks to the
daughter boards and the 200 MHz sampling clocks are both generated
by the "clock jitter clean" chip (LMK0481). I did not have time yet to
check the configuration of this chip, but probably yo
Hi,
please double check on that, as I am not 100% sure.
As far as I was able to figure out, the LO is generated from the
Daughterboard internal 200 MHz reference (which is dirived from the 10
MHz), but is divided by 4 for some reason, so you get multiples of 50
MHz. This will also induce a ran
