Hello Wade,
The key is that Ryan tried to run synthesis again via Vivado gui.\
>From my experience this won’t work because some build parameters (like the
>mentioned macro definition) are passed together with synthesis command
>(synth_design).\
If there is another way to make it work other than
Oh, interesting. I'd like to understand why it doesn't work for some
people. This FPGA gets built quite regularly by myself and others without
this issue.
Wade
On Fri, Aug 25, 2023 at 9:53 AM wrote:
> Hello,
>
> The undefined *RFNOC_EDGE_TBL_FILE* macro is a typical error when you try
> to buil
Hello,
The undefined **RFNOC_EDGE_TBL_FILE** macro is a typical error when you try to
build a Vivado project generated for X410.
The reason is that the macro is not passed correctly when synthesizing the
Vivado project. My workaround was to use synth_design command generated by UHD
X410 Makefi
Hi Ryan,
What was the problem/error message that suggested that folder wasn't being
pulled in properly? The "syntax error" implies that the
`RFNOC_EDGE_TBLE_FILE definition isn't being set correctly, but the
makefile should pass that in based on the target you're building.
Did you make modificati
