Here's a quick explanation. FPGAs have clocks that control the transfer of
data between its internal registers. The Xilinx Vivado tool does a timing
check during build to make sure that the paths from each driving register
to each receiving register is not too long for the specified clock period.
W
On 22/12/2022 20:11, AERMAN TUERXUN. wrote:
Hi,
I am building a custom RFNoC block on USRP X310.
When I was trying to build bitstream, after almost two hours
processing, it gave me the error as below.
Do you have any idea what timing constraints are?
Is that because the custom IP is too large
