[USRP-users] Re: Starting FPGA development on Ettus N321

2023-01-17 Thread Brian Padalino
On Tue, Jan 17, 2023 at 11:04 AM wrote: > I have the vivado project saved now, thanks for your help! > Glad it worked out for you. For the simulator files, I am a bit lost as to how it should be created? > > I am following these instructions to build the simulator files > https://files.ettus.co

[USRP-users] Re: Starting FPGA development on Ettus N321

2023-01-17 Thread jmaloyan
I have the vivado project saved now, thanks for your help! For the simulator files, I am a bit lost as to how it should be created? I am following these instructions to build the simulator files https://files.ettus.com/manual/md_usrp3_sim_writing_sim_makefile.html. I tried running the viv_simul

[USRP-users] Re: Starting FPGA development on Ettus N321

2023-01-16 Thread Brian Padalino
Glad it worked out. It builds an in memory project only I believe. You can load up the GUI by adding GUI=1 to the make command. From there, you can save off the project if you like. You can also only check syntax with CHECK=1. Check the bottom of the Makefile for some other supported command l

[USRP-users] Re: Starting FPGA development on Ettus N321

2023-01-16 Thread jmaloyan
This worked! Thanks. Do you know if the makefile generates a vivado project (.xpr file) or does it only produce a final bitstream and its reports? ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...

[USRP-users] Re: Starting FPGA development on Ettus N321

2023-01-13 Thread Brian Padalino
Your git output says there are local modifications and then you describe them but say it's all clean. Strange? Anyway, yes - you need to install a patch from Xilinx. Follow this: https://support.xilinx.com/s/article/76780?language=en_US Download the ZIP file linked there and follow the insta

[USRP-users] Re: Starting FPGA development on Ettus N321

2023-01-13 Thread jmaloyan
When I type ‘git status’, it says there are no changes, I have dumped the output of git status below.… > HEAD detached at v4.3.0.0 > > Changes not staged for commit: > > (use "git add ..." to update what will be committed) > > (use "git restore ..." to discard changes in working directory) >

[USRP-users] Re: Starting FPGA development on Ettus N321

2023-01-13 Thread Brian Padalino
Vivado locks IP if it's been targeted for the wrong device, or generated with the wrong version of the software. Did you receive any warnings about the wrong version of Vivado being used? Are you running in a clean UHD repo (git status shows no changes)? I've run into this issue when things were

[USRP-users] Re: Starting FPGA development on Ettus N321

2023-01-13 Thread jmaloyan
Hello, I have run the setupenv. build-ip is a folder that is made when the makefile(uhd/fpga/usrp3/top/n3xx/Makefile.inc) is run. Removing it does not do anything, but I did try commenting out include statements in the Makefile. I tried commenting hb47_1to2 in the makefile, and it proceeded si

[USRP-users] Re: Starting FPGA development on Ettus N321

2023-01-12 Thread Brian Padalino
I am assuming you also sourced setupenv.sh in the n3xx directory? If you remove the n3xx/build-ip/xc7z100ffg900-2/hb47_1to2 directory and try again, does it still fail? Brian On Thu, Jan 12, 2023 at 6:35 PM wrote: > Hello, > > > I am trying to create a Vivado environment for the ettus 321, how