Thank you very much! You were right. I made a mistake with the clock in my
module.
El mié, 28 sept 2022 a las 4:19, Wade Fife () escribió:
> There's not enough information in the screen shot, but I think the output
> of the double synchronizer is on a different clock domain than flop flop
> (da
There's not enough information in the screen shot, but I think the output
of the double synchronizer is on a different clock domain than flop flop
(dato_entrada) being reset by it.
The reset signal needs to be driven by the same clock as the flip flop
being reset, otherwise Vivado can't ensure tha
On Tue, Sep 27, 2022 at 7:21 AM wrote:
> Hi every one!
>
>
> I am facing some problems with reset timing violations. This is is one for
> example, and i have a fews. I tried to instantiate the reset signal but it
> didn work. I don know how to fix it. On the other side, i have seen a reset
> gene
