Thanks Wade, then I'll check my clock domain crossings, guess I need a
fifo between them.
Kind Regards,
Maria
El mar., 14 jun. 2022 20:47, Wade Fife escribió:
> Hi Maria,
>
> In the timing paths, take a look at the source clock and destination
> clock. Are they the same clock? If not, then may
Hi Maria,
In the timing paths, take a look at the source clock and destination clock.
Are they the same clock? If not, then maybe you haven't handled the clock
domain crossings correctly. If you lowered the clock frequency, the number
of failing paths should go down, but if there are clock crossin
Hi again Wade,
After making some synthesis with and without the clock wizard ip, I have
observed that there is higher timing paths for those which use the ip
rather than the ones which don't.
I am lowing the clock for the design so I would expect the opposite
behaviour. Alongside with the verilog
You're right. It really depends on the IP. Some are very complicated
(hundreds of files) and it makes sense to try to use the XCI and let Vivado
do the work of figuring out all the dependencies. For the clk_wiz, I think
it makes more sense to just reference the .v files generated by Vivado, or
just
Hi all,
Thanks for your answers.
Wade, you are correct, I am trying to instance a clock wizard for an x310
project. In my VHDL/Verilog Makefile.srcs, I have included the clk_wiz_0.v
and clk_wiz_0_clk_wiz.v files as you said and, for now, synthesis is not
complaining, so it seems to work (I guess
Hi Maria,
Which IP are you trying to include? And is it failing when trying to
simulate or only when building the FPGA? Some IP are easier to include than
others. From your examples, it looked like you were trying to include the
clock wizard. For that IP I usually just copy the MMCM or PLL code th
Ok, I'll take a look. I had a question for creating your custom RFNOC block
do you use rfnocmodtool creator?
I think for using an IP core from Xilinx in your
rfnoc_rfnocblock_blockname.v, you should see a folder in the UHD driver?
I worked with x300 series RFNOC block, In a folder on this path
(/ho
Hi,
Thanks for the answer.
I think that what I'm trying to do should be possible since the addsub
example has an option for a hls instance. Maybe I have not explain myself
well.
I have a top level module which includes several .vhd sources alongside
with an ip from xilinx. I can instance this top
Hi, You should not expect that integrate or add Xilinx IP core directly to
RFNOC blocks, Even If you be a master in Verilog...
If you see the UHD source code you will realize that UHD is an RFNOC
framework for USRP ...
For working with the RFNOC UHD framework you should know more details:
1)Please
Hi Maria,
I apologize but I am not very experienced with these matters. I am able to
copy the rfnoc-example folder to an OOT location and build it and I know it
has both OOT and in-tree IP options. In the past I have successfully run
the 'make ' and also built an image such as "make ".
But, outsid
Hi Rob,
I try to put these lines in the makefile.srcs inside my_block/fpga folder
as in the rfnoc example:
#RFNOC_OOT_SRCS += $(abspath $(addprefix ${RFNOC_EXAMPLE_DIR},
#my_other_module.v \
#ip/my_ip_core/my_ip_core.xci \
#))
I add my .xci IP to this folder and give the name of the IP as a
rfno
Hi Maria,
The rfnoc-example folder within the UHD tree shows an example of how to add
an out-of-tree IP block. Did you look at this yet?
Rob
On Wed, Jun 1, 2022 at 5:12 AM Maria Muñoz wrote:
> Hi all,
>
> I'm trying to synthesize a design that includes a vivado ip core inside.
> Normally, I add
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