Tim Vancauwenbergh
From: Marcus Müller
Sent: Thursday, March 14, 2024 11:24:19 AM
To: Tim Vancauwenbergh ;
usrp-users@lists.ettus.com
Subject: Re: [USRP-users] Re: B210: synchronise USRP Sink & USRP Source blocks
in GNU RC
Negative times don't make much sen
024 3:42:33 PM
*To:* usrp-users@lists.ettus.com
*Subject:* [USRP-users] Re: B210: synchronise USRP Sink & USRP Source blocks in
GNU RC
Hi Tim,
that delay will vary, the way you're currently are setting things up, and
there's likely
going to be an underflow on the transmitter side, b
M
To: usrp-users@lists.ettus.com
Subject: [USRP-users] Re: B210: synchronise USRP Sink & USRP Source blocks in
GNU RC
Hi Tim,
that delay will vary, the way you're currently are setting things up, and
there's likely
going to be an underflow on the transmitter side, because you star
Hi Tim,
that delay will vary, the way you're currently are setting things up, and there's likely
going to be an underflow on the transmitter side, because you start both "roughly" at the
same time, but it takes some time for RX to produce some samples, while TX expects samples
to be ready.
S
