Christian,
If memory serves me correctly the missing pages are due to that portion of the
design using a proprietary NI ASIC that handles the PCIe interface and the
flash storage of the FPGA config data. Since it handles config it would be
reasonable to assume that circuit also supplies initial
I can answer the question related to the padding. I am not sure about the
rest.
Ettus Padding: An ethernet frame has 6 bytes of destination MAC address and
6 bytes of Source MAC address. Since we use 64 bits/8 bytes of data in one
clock cycle, we add a 6 byte padding in front of the ethernet packe
Ian and Sugandha,
thank you very much for your comments and also for the attached file.
Sadly, another three questions remain for the moment:
1. In the attached file, there is a series of 48? bits named "Ettus
Padding". Is this an Ettus specific bit sequence and where can I find
information o
Christian,
CHDR packets are encapsulated in UDP/IP between Host and USRP. See the
attachment.
PHY+ MAC functionality live under the x300_sfpp_io_core. However these blocks
do not encapsulate/decapsulate the network packets.
All the ethernet/IP/UDP framing fields are added by chdr_eth_framer on
Hey Sugandha,
thanks for your help. I apologize for the incredible delay from my
side, but back to my question.
We want to port a hole IP solution from some proprietary hardware to
the USRP and evaluate the costs (mainly development time) of migrating
our IP to RFNoC vs. a custom image.
The crux
