Hi Derek,
Thank you again for your explanation. I will start my rfnoc development
with something else and may do this modification to a later time.
Regards,
andreas
On 31.07.2018 11:56, Derek Kozel wrote:
Hi Andreas,
The timekeeper lives inside of the Radio block. However, after looking
mo
Hi Andreas,
The timekeeper lives inside of the Radio block. However, after looking more
into the code, the DUC and DDC do already read the timestamp data from the
CHDR packets. You could modify the DUC and DDC to use the timestamp data to
jump the phase accumulator's value to compensate for the id
Thank you Derek for the explanations,
As workaround I will have to send continuously.
Just a curiosity, as I am very new in rfnoc development: Where is the
timing of the bursts done in the FPGA? In the DmaFIFO block? And would
it be possible to modify this block such that it sends zeros while n
Hello Andreas,
The digital frequency offset is handled in the DUC block which does not run
in the same clock domain as the Radio block. The phase accumulator register
will only increment when samples are being processed. The simplest way to
cause the phase accumulator to continuously run (from the
Hello all,
I am using a USRP X310 with a UBX-160 daughterboard. The transmit signal
on port TX/RX is attenuated and looped back to the receiver on port RX2.
Every millisecond I am sending a short rectangular pulse (about 10 us long)
using the 'time_spec' attribute of the transmit meta-data
('st
