Hello Artyom,
Unfortunately, this is something we are aware of and has to do with the
high utilization that the DDCs and DUC blocks are taking. We are actively
working on reducing the FPGA utilization of these blocks in order to make
this build possible.
Regards,
- Nicolas
On Sun, May 20, 2018
2017.4
вс, 20 мая 2018 г., 17:25 Marcus Müller :
> Interesting!
> What's your Vivado version?
>
> On 20 May 2018 13:44:28 GMT+02:00, Artyom Asadchy
> wrote:
>>
>> Hello, Marcus.
>> Yes. this is the unmodified image. I clone it from https://github.com/
>> EttusResearch/fpga, checkout to rfnoc-dev
Interesting!
What's your Vivado version?
On 20 May 2018 13:44:28 GMT+02:00, Artyom Asadchy wrote:
>Hello, Marcus.
>Yes. this is the unmodified image. I clone it from
>https://github.com/EttusResearch/fpga, checkout to rfnoc-devel (in my
>case
>commit d1d683bcd87bd3cea56f9654152b53e4830db612), tha
Hello, Marcus.
Yes. this is the unmodified image. I clone it from
https://github.com/EttusResearch/fpga, checkout to rfnoc-devel (in my case
commit d1d683bcd87bd3cea56f9654152b53e4830db612), than navigate to
"usrp3/top/e300", run "source setupenv.sh" and "make E310_sg3".
Best regards, Artyom.
2018
Hello Artjom,
Is this the unmodified image? The error basically complains about too much
logic to put on the FPGA, and that doesn't happen with our stock images. How
are you building this?
Best regards,
Marcus
On 19 May 2018 20:16:40 GMT+02:00, "Артем Асадчий via USRP-users"
wrote:
>Hi every
Hi everyone,
I've got a problem, when try to build E310_sg3.bit:
ERROR: [Place 30-487] The packing of instances into the device could not be
obeyed. There are a total of 13300 slices in the pblock, of which 7850
slices are available, however, the unplaced instances require 9752 slices.
Please ana
