Re: [USRP-users] B200/ADI9361 - Influence of master clock rate on EVM

2018-05-19 Thread Sylvain Munaut via USRP-users
Or actually it might just be that the usrp_dev->get_rx_bandwidth() call doesn't return what's really programmed. Looking at _setup_rates, the var _baseband_bw is setup there. In case (1) I have rate=N and divfactor=32 (as I mentionned in the first mail, I force FIR 4x interp here) and _baseband_b

Re: [USRP-users] B200/ADI9361 - Influence of master clock rate on EVM

2018-05-19 Thread Sylvain Munaut via USRP-users
Hi, > That’s strange, by default the analog filters should be being configured from > the master_clock_rate to have optimal bandwidth for the master_clock_rate on > the assumption your signal uses the bulk of that bandwidth. That's what I would have thought. Maybe I'm just probing it too early

Re: [USRP-users] B200/ADI9361 - Influence of master clock rate on EVM

2018-05-19 Thread Ian Buckley via USRP-users
That’s strange, by default the analog filters should be being configured from the master_clock_rate to have optimal bandwidth for the master_clock_rate on the assumption your signal uses the bulk of that bandwidth. UHD version? > On May 19, 2018, at 2:37 AM, Sylvain Munaut via USRP-users > wro

[USRP-users] B200/ADI9361 - Influence of master clock rate on EVM

2018-05-19 Thread Sylvain Munaut via USRP-users
Hi, I'm comparing two cases that, in theory (at least in my understanding of things), should yield the same result but don't :) 1) I'm sending data to the USRP at sample_rate N with master_clock_rate N and the ADI has FIR 4x, HB 2x,2x,2x 2) I'm sending data to the USRP at sample_rate N with mast