> [00:04:26] Process terminated. Status: Failure
>
> Thanks,
> Jim
>
>
>
> ----------
> *From:* USRP-users on behalf of Jim
> Palladino via USRP-users
> *Sent:* Thursday, October 15, 2020 1:13 PM
> *To:* usrp-users@lists.ettus.com
>
From: USRP-users on behalf of Jim
Palladino via USRP-users
Sent: Thursday, October 15, 2020 1:13 PM
To: usrp-users@lists.ettus.com
Subject: [USRP-users] Adding Xilinx IP to custom RFNoC block
Hello,
I'm trying to add a Xilinx DDS to a custom RFNoC bl
Hello,
I'm trying to add a Xilinx DDS to a custom RFNoC block (using UHD 4.0 and
associated gr-ettus repo). To do this, I started building the FPGA image using
the GUI option, stopped the build shortly after Vivado opened, and saved a
Vivado Project. Then, in Vivado I configured/added a Xilinx
