Hi,
At this point, I would suggest using Vivado ILA (aka Chipscope) to see what
is going on. We have a tutorial on how to do this here:
https://kb.ettus.com/Debugging_FPGA_images. Try Chipscoping all the AXI
Stream signals in your block and then post a screenshot. I can take a look
and try to advi
Hello everyone,
We are designing a pseudo-random data generator using an LFSR register with
the Fibonacci method in RFNoC, to be implemented into the E310, taken as
reference the "SIGGEN" block provided in the RFNoC library. The problem is
that we do not have any data output and in the console of
