[USRP-users] Re: RFNOC TB

Sorry, my mistake. I emptied the send_samples before sending it. Now it is working. Thanks! ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com

[USRP-users] Re: RFNOC TB

Hi, Sorry to bother again. I have tried the next code but vivado freezes when it reaches recv_items. What i want is to read the file and send every time i have a packet of 64. The txt file is something like this: 69 58 \-53 268 … `FILE=$fopen("input.txt","r");` `send_samples = {}

[USRP-users] Re: RFNOC TB

How can i do that? i have tried to read a file in the process but the simulation failed. Can you give me some advice? Thanks in advance ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettu

[USRP-users] RFNOC TB

Hi every one, I would like to use the rfnoc testbench but with my own signals and remove this condition: \ `` `ASSERT_ERROR( `` ` sample_out == sample_in,` ` $sformatf("Sample %4d, received 0x%08X, expected 0x%08X",` `i, sample_out, sample_in));` In conc

[USRP-users] Strange memory behavior

Good morning. I am writing because I am working with the USRP E320 RAM and the AXI_RAM_FIFO module and I am having, in my opinion, strange behaviors in memory. My goal is to store in memory the data I receive from a point, let's call it POINT A, and to get this data out from another point, POIN

[USRP-users] AXI_RAM_FIFO doesn´t return any information

  Hello everyone, I am trying to make use of axi_ram_fifo together with a rfnoc block of my own. Basically, my block receives 2 inputs (one from outside and one from FIFO) and sends 2 outputs (one to outside and one toFIFO) . These are converted to the payload and function of my block is to sto

[USRP-users] Simulation after synthesis or implementation

Hi everyone, I was wondering if it is possible to make a simulation,, and how, after sythesis or implementation because i am not getting the results that i was expecting and i don´t know why. Thanks in advance. Adrián Campos ___ USRP-users mailing li

[USRP-users] Re: UHD_IMAGE_LOADER load another .bit

I tried but i didn´t work. Anyway, i have no problems loading others projects only with this. ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.ettus.com

[USRP-users] Re: UHD_IMAGE_LOADER load another .bit

Hardware: e320 Command: uhd_image_loader --args "type=e3xx,mgmt_addr=ip,fpga=1G" --fpga-path usrp_e320_fpga_1G.bit And yes, i restarted. ___ USRP-users mailing list -- usrp-users@lists.ettus.com To unsubscribe send an email to usrp-users-le...@lists.et

[USRP-users] Synthesis of Xilinx IP in RFNOC

Hi every one! I´m facing some problems to synthesize a proyect that has a Xilinx IP, a FIFO Generator. I´ve been following this example but it didnt work. https://github.com/EttusResearch/uhd/tree/master/host/examples/rfnoc-example The synthesis return me this: 'fifo_generator_0' has undefined

[USRP-users] Reset Timing Violation

Hi every one! I am facing some problems with reset timing violations. This is is one for example, and i have a fews. I tried to instantiate the reset signal but it didn work. I don know how to fix it. On the other side, i have seen a reset generation in a noc shell and i was wondering if i have