[USRP-users] Time Spec to control transmission at 100MSps USRP X310

2018-02-25 Thread Karan Suri via USRP-users
Hi usrp-users, I recently started working on a *multilateration* based localization scheme to detect a tag USRP (reader). The 100MHz OFDM packets (STF +LTF + information bits) are* transmitted at 100 MSps to the reader* via the anchor hub USRP X310. I am new to handling the time_spec and other fea

[USRP-users] How to Access a user register in fpga of X310 using UHD (3.10.2)

2017-08-31 Thread Karan Suri via USRP-users
Hello Users I recently stumbled onto a problem. I need to implement a gain control mechanism by left shifting bits of the received data, when the rx power is considerably low. I need to define a settings register which controls the shift amount, but I need to get access to this setting register us

[USRP-users] Synchronised RX and TX control in X310

2017-08-20 Thread Karan Suri via USRP-users
Hello usrp-users. I was successfully using a source code capable of transmitting and Receiving OFDM packets in USRP X310. The anchor USRP transmits an OFDM packet at frequency f1 , it is received by a tag USRP which loops back the received OFDM packets at frequency f2. The same OFDM packet is then

[USRP-users] Using both TX/RX and RX2 ports on the same daughter board to receive signal simultaneously

2017-08-02 Thread Karan Suri via USRP-users
Hi, I'm trying to using both TX/RX and RX2 ports on the same daughter board of X310 to receive signal at the same time. On the host side, I tried to create a new recv_to_file thread inside the main thread(which will execute another recv_to_file). However, the terminal will show the error "0/Radio_0

Re: [USRP-users] Support with UHD C++ API

2017-08-02 Thread Karan Suri via USRP-users
For minimum data loss at 50MSps, you have to use a 10G cable , Data rate with 1G is limited to ~33 MSps which rounds off to 28 MSps (integral decimation). Karan Suri University of Michigan On Aug 2, 2017 3:56 PM, "Derek Kozel via USRP-users" < usrp-users@lists.ettus.com> wrote: > Hello Snehasish

Re: [USRP-users] Sampling ADC/DAC at a different sampling rate compared to the FPGA-host data rate

2017-07-21 Thread Karan Suri via USRP-users
help. Karan Suri University of Michigan On Jul 21, 2017 11:52 AM, "Marcus Müller via USRP-users" < usrp-users@lists.ettus.com> wrote: > Hi Karan, > > what USRP model are we talking about? > > Best regards, > > Marcus > > On 20.07.2017 07:51, Karan Suri vi

[USRP-users] Sampling ADC/DAC at a different sampling rate compared to the FPGA-host data rate

2017-07-19 Thread Karan Suri via USRP-users
Hello USRP Users I was able to develop an *FPGA based loop back which directs the raw ADC data to the DAC* . The TX transmits whatever it sees on the receive signal path. The loop back works as expected for sampling rates upto 30 MSps but it fails to loopback received signals at a *higher sampling

Re: [USRP-users] Compatibility issues of UBX-160 with X310

2017-07-12 Thread Karan Suri via USRP-users
an Suri University of Michigan Masters of Science IC-VLSI On 12 July 2017 at 03:27, Marcus Müller via USRP-users < usrp-users@lists.ettus.com> wrote: > Dear Karan, > > could you share the verbatim output of uhd_usrp_probe (including the very > first line)? > > Best regards,

[USRP-users] Compatibility issues of UBX-160 with X310

2017-07-11 Thread Karan Suri via USRP-users
Hi I recently got two UBX160 daughter boards to work in the ISM band of 5.8 GHz. I am not able to detect these daughter boards at all. I am using uhd_version 3.10 I can correctly detect all my other types of daughter boards (CBX, SBX , WBX). I read through some of the mailing lists and came across