ons.
>
>
>
> Robert
>
>
>
> *From:* USRP-users [mailto:usrp-users-boun...@lists.ettus.com] *On Behalf
> Of *Kai-Uwe Storek via USRP-users
> *Sent:* Wednesday, February 13, 2019 4:53 PM
> *To:* usrp-users@lists.ettus.com
> *Subject:* [USRP-users] N310 Images with exter
Hey Folks,
I'm struggling with the external LO feature of my N310. This issue might be
related to
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2018-April/056233.html
.
Setup:
Signal generator outputs a continuous wave at 2.002 GHz (-50dBm) to the RX2
of RF0. With internal LO everyt
Is there something else I can in order to support the investigation of
the problem? Is it useful to open a new issue on github?
2017-10-20 19:23 GMT+02:00 Marcus D. Leech via USRP-users
:
> On 10/20/2017 04:20 AM, Kai-Uwe Storek via USRP-users wrote:
>>
>> Hey Marcus and Brent,
&
f any; for practically all
> daughterboards the TX LO and RX LO synthesizers are the same. The digital
> mixing is only used to amount for the difference between the closest element
> from the set of discrete frequencies the hardware can generate and what RF
> frequency you requested.
Hey,
the attached flowgraph simply generates a sine which is transmitted
and received by the same USRP in a loop (30dB attenuation + coax cable
between tx and rx port). I used the following USRPs:
- B210
- X300 (1G Eth)
- X310 (1G Eth)
On the Rx side I just added a time sink to view the complex
ph with UHD 3.10.2 causes again
100% CPU load on a single core over the entire time.
2017-10-19 23:05 GMT+02:00 Marcus D. Leech via USRP-users
:
> On 10/19/2017 10:25 AM, Kai-Uwe Storek via USRP-users wrote:
>>
>> Hey,
>>
>> after experiencing some problems (time outs,
Hey,
after experiencing some problems (time outs, etc) with the current UHD
develop version (master branch) I changed the UHD version to 3.10.2
(maint branch, #122bfae).
To do so, I just used the prefix recipe gnuradio-stable via pybombs.
Now I'm not able to transmit even low bandwidth signals.
Hey,
if I use an instantiation of rfnoc-devel/usrp3/lib/rfnoc/cmul.v in my
design, the compilation / elaboration process (make
noc_block_myblock_tb) fails with:
ERROR: [VRFC 10-2063] Module not found while
processing module instance
[/home/labor/gr_prefixes/rfnoc/src/uhd-fpga/usrp3/lib/rfnoc/cm
