Hi Jonathon,
Thank you for replying back, I have watched both videos RFNoC 3 and 4 and
based on them along with the UHD 4 guide, I noticed that the DmaFIFO was
used in some cases.
For instance, based on the video RFNoC 3, in the fosphor demo with 100M
Rate, DmaFIFO and RFNoC FIFO blocks were us
Thank you, I will try this and publish my findings.
On Tue, Mar 23, 2021 at 6:16 AM Chang, Kaixin
wrote:
> Hi,
>
>
> in c++ there is something like
>
> virtual void connect(const block_id_t& src_blk,
> size_t src_port,
> const block_id_t& dst_blk,
> size_t dst_port,
> bool skip_property_propagat
Hi all,
I am currently following the Getting started UHD 4 guide and when building
a fpga image running the following command:
* rfnoc_image_builder -F ~/uhd/fpga/ -I ~/rfnoc-ws/rfnoc-test/rfnoc/blocks
-y ~/rfnoc_ws/rfnoc-test/rfnoc/icores/demo_x310_rfnoc_image_core.yml -t
X310_XG*
I get the fol
Got it.
Thanks.
On Tue, Mar 16, 2021 at 7:00 PM Wade Fife wrote:
> You have to specify context_fifo_depthwhen using axis_pyld_ctxt. See, for
> example, the addsub block.
>
>
> On Tue, Mar 16, 2021 at 11:56 AM Julian Casallas
> wrote:
>
>> Jonathon,
>>
>
port and axis_pyld_ctrl are the correct choices. One
> exception is when writing a block that changes sampling rate. You may want
> to use axis_chdr so you can easily interface with the axi_rate_change
> module. The DDC / DUC are examples of that use case.
>
> Jonathon
re the number of ports is
> based on a parameter called NUM_PORTS.
>
> Jonathon
>
> On Tue, Mar 16, 2021, 10:15 Julian Casallas
> wrote:
>
>> Hello,
>>
>> I went through the Getting Started with RFNoC UHD 4 guide and I
>> followed the RfNoC 4 WorkShop
Hello,
I went through the Getting Started with RFNoC UHD 4 guide and I followed
the RfNoC 4 WorkShop - GRCon 2020 to design a RFNoC block, this is what I
did:
1. Created the gain block and it works fine following the RFNoC 4 video. I
checked the HDL files, and I could see the interfaces payload
