best regards, Felix
> On Wed, Jan 8, 2020 at 8:00 AM Felix Greiwe via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Hi EJ,
>>
>> thank you for your answer! To make my error more traceable, I created a
>> new OOT Module and added the default gain block
rfnoc-ootexample
>
> I might suggest trying to check that out and see if you can build with one
> of those blocks first, then modify for your purposes?
>
> Also, one other thing to mention is you might have some luck debugging the
> uhd_image_builder.py to see where it's going wron
Hello again,
has no one an idea? I have still not managed to get it working..
I would take any advice!
Best regards,
Felix
> Hello together,
>
> recently I installed the whole UHD/GNU-Radio Toolchain on a fresh install
> of Kubuntu 18.04 LTS. I followed the instructions from
> https://kb.ettus
Hello together,
recently I installed the whole UHD/GNU-Radio Toolchain on a fresh install
of Kubuntu 18.04 LTS. I followed the instructions from
https://kb.ettus.com/Getting_Started_with_RFNoC_Development
and used the Pybombs install.
(I ran into a lot of problems there and had to install a lot o
data?
Best regards,
Felix
> On Thu, Sep 19, 2019 at 9:39 AM Felix Greiwe via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> Hello together,
>>
>> I have some questions concerning clock speeds and the corresponding data
>> rates on a USRP x310
Hello together,
I have some questions concerning clock speeds and the corresponding data
rates on a USRP x310 (FPGA). As far as I know, there are two different
clock speeds on the FPGA, the ce_clk=200MHz, and the bus_clk - I did not
find clock speed for this one.
Is it true, that the ce_clk drive
Is it still the same process? (When I
>> use
>> the UHD_USRP_SINK Block with two inputs, the phase seems to be constant
>> with each restart even without tuning them with timed commands. This
>> behauviour is the goal; only that I want to use RFnoC instead)
>>
>>
generated by GRC. Here's a relevant GRC manual section
>> [1],
>> and an example snippet of tuning with timed commands in the UHD Manual
>> [2].
>> Doing this correctly should ensure that you are able to keep a
>> consistent
>> phase offset between your TX
treams are being fed data from a single source. I don't
> think this will solve your problem, but if the blocks are doing the same
> thing, may help take a variable out of the equation.
>
> Sam
>
> [1]
> https://www.gnuradio.org/doc/doxygen/classgr_1_1uhd_1_1usrp__block.html
> [2
Hello together,
I am trying to transmit one complex cosine from both TX - Antenna of my
USRP-x310 with two UBX-160 Daugtherboards. I am transmitting a cosine with
the frequency of 100 kHz and the center frequency of my RFNoC Radio Blocks
is 2.45 GHz. So basically I see a peak at 2.45 Ghz + 100 kHz
Hello together,
recently i wanted to change the IP-Adress of my USRP device, because i
wanted to connect two USRP x310 to the same host computer. I followed the
instructions at the uhd-manual to change the device IP:
https://files.ettus.com/manual/page_usrp_x3x0.html#x3x0_setup_change_ip
and cha
Hi,
i found myself not to be familiar with the Core Concept of interpreting
Data in FPGA's as IQ-Data. After i partitioned my 32 Bit Input Data in 16
Bit I and 16 Bit Q Data, and additionally edited my testbench similar to
the addsub testbench of one of the pre-installed rfnoc-blocks, my
testbench
Hello together,
recently i started RFNoC development using an USRP x310. After finishing
the RFNoC getting started Guide i created an OOT Module including VHDL.
First i simply forwarded the Input Data to the output which worked just
fine. After that i wanted to add a constant, for example 5_dec.,
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