[USRP-users] low send data rate - x310- VM

Hi everyone, I'm working on usrp x310 . After few experiment with the system, i tried to send data from file source (gnuradio) to my own OOT rfnoc block that do nothing (tready is always on '1' and one register that count axi_stream data valid) i saw that the average send rate to the FPGA is 320KB

Re: [USRP-users] reading from ddr3 - high latency

> Hi Daniel, > > The latency will be dominated by Xilinx's MIG IP that interfaces with the > DDR RAM. You can try looking at Xilinx's documentation and see what > parameters you can change to improve latency. > > Jonathon > > On Sat, Oct 3, 2020 at 9:10 AM Daniel Oz

[USRP-users] reading from ddr3 - high latency

Hi everyone, I'm working on usrp x310 . I create my own version of the replay block . I almost didn't change anything in the 2 state machines in the axi_replay.v . everything worked fine but then i saw in the chipscope that my replay block got data after 110 clks. (although the read ctrl ports in

[USRP-users] crossbar architecture

Hi everone , Im working on usrp x310 . I have tried to ifind what is the architecture of the axi crossbar and i didnt found any thing in the auto generated vivado project . Is it Shared Write and Read Address Arbitration? [image: axi_crossbar_shared.png] Or is it fully parallel? [image: axi_crossb

[USRP-users] rfnoc data type‏

hi everyone , i have several question regarding to the rfnoc data type: 1. what is the change if i pass data through rfnoc block as a byte type or as a sc16? Is there a change inside the fpga ? 2. At least in my uhd version the rfnoc: duc has only one type which is fc32 . can i change it to sc16

Re: [USRP-users] rfnoc questions:‏‏

of the packetized crossbar >> because you need absolute minimal latency, you could theoretically add >> side-channels between rfnoc blocks, or insert your logic into a different >> part of the design (like the radio block, perhaps). I have heard of these >> strategies working for

Re: [USRP-users] rfnoc questions:‏‏

I have heard of these > strategies working for some people, but I really wouldn't recommend that > for a beginner rfnoc user since you would effectively break all the helpful > utilities that come along with rfnoc as-is (automatic builds, > reusability/modularity of rfnoc blocks,

[USRP-users] rfnoc questions:‏‏

Hi everyone, Im just started developing on the usrp X310 platform and i have some questions : 1. Is the crossbar is capable to transfer data between 2 rfnoc blocks at maximum rate of the crossbar clock ?(bus_clk=187.5MHZ) 2. if i have this theoretical chain : rfnoc: block1 -> rfnoc: block2 -> r

[USRP-users] Use most of the ddr3 space in x310

Hello everyone , I want to load a file using the replay block that will consume almost all the space of the ddr3 on the device . I saw that replay block has a address range of 32mib which is not enough at all . How can i change the space address of the replay block and what is the max size i can p

[USRP-users] Questions regrading to axi wrapper

Hi , I'm developing OOT rfnoc block that read and write data from the ddr3 ram. While exploring for options in replay block I saw that the axi_wrapper data vector (m_axis and s_axis) input and output is a 64bit vector while in the OOT rfnoc block format and and in others noc blocks the data vector

[USRP-users] Writing and reading from ddr3 in usrp x310

Hello, Im trying to write and read data from the ddr3 ram in the usrp x310 using the fpga. I wasn't able to find if there is any other blocks that use the ram (in the defualt image ) . Also are there any rfnoc blocks that uses the ram ? Thx ___ USRP-user