Ian and Sugandha,
thank you very much for your comments and also for the attached file.
Sadly, another three questions remain for the moment:
1. In the attached file, there is a series of 48? bits named "Ettus
Padding". Is this an Ettus specific bit sequence and where can I find
information o
further questions.
Cheers
Sugandha
On Tue, Apr 4, 2017 at 6:54 AM, Christian Lenz via USRP-users <
usrp-users@lists.ettus.com> wrote:
Hi,
I’m currently evaluating the effort/feasibility of running a custom FPGA
image in a USRP X3x0. One thing left is the connection Host PC <—> FPGA
