[USRP-users] Re: KAS kirkstone build of ni-titanium-rev5 on x410 with Vitis-AI Library and DPU drivers: Mainline kernel incompatible with zocl DPU driver; possible to use linux-xlnx kernel and make ti

2024-10-01 Thread perper
Hello, I ported USRP X410 code to ZCU111. As the NI/Ettus kernel didn’t work straight away (i.e. because of device-tree and bootloader issues) I started from booting with a linux-xlnx kernel that I had from Petalinux together with device-tree for ZCU111. I was able to use that kernel to some p

[USRP-users] Re: rfnoc_image_builder on UHD 4.7

2024-10-01 Thread chris.pineda--- via USRP-users
I’ve run into this problem with UHD 4.6. That specific function got removed in the latest version so in order to make it work, I had to downgrade the ruamel.yaml version with the following: > pip install "ruamel.yaml<0.18.0" Once you downgrade it, it should work. __

[USRP-users] rfnoc_image_builder on UHD 4.7

2024-10-01 Thread Ryan Marlow
Hi All, It's been some time since I've tried to build anything rfnoc related. I am trying to build an image for X310 using the latest UHD 4.7 on Ubuntu 22.04. I think I installed the necessary prerequisites including ruamel.yaml. > pip3 show ruamel.yaml > Name: ruamel.yaml > Version: 0.18.6 > Summ

[USRP-users] Re: KAS kirkstone build of ni-titanium-rev5 on x410 with Vitis-AI Library and DPU drivers: Mainline kernel incompatible with zocl DPU driver; possible to use linux-xlnx kernel and make ti

2024-10-01 Thread Marcus D. Leech
On 01/10/2024 12:09, mruane--- via USRP-users wrote: Hi all! I’m an FPGA developer, dragged into the Yocto world a few years ago with the move to Zynq and ZynqMP architectures. As a research group, we mainly develop on Xilinx dev boards like the ZCU102 MPSoC, and ZCU111 RFSoC. Having recen

[USRP-users] USRP-2974 FPGA core temperature

2024-10-01 Thread cyberphox
Hi Ettus Team I have a couple of USRP-2974 that have a higher than normally seen FPGA core temp. Normally I see around 58-60C something like that. But on two units I get around 70-75C. The max temp is 85C for the FPGA, so getting close.In all cases, the units are at a room temperature, lo

[USRP-users] KAS kirkstone build of ni-titanium-rev5 on x410 with Vitis-AI Library and DPU drivers: Mainline kernel incompatible with zocl DPU driver; possible to use linux-xlnx kernel and make titani

2024-10-01 Thread mruane--- via USRP-users
Hi all! I’m an FPGA developer, dragged into the Yocto world a few years ago with the move to Zynq and ZynqMP architectures. As a research group, we mainly develop on Xilinx dev boards like the ZCU102 MPSoC, and ZCU111 RFSoC. Having recent success adding the Xillinx Deep-Learning Processor (DP

[USRP-users] Re: Rfnoc loopback in uhd 4.6

2024-10-01 Thread perper
Hello Maria, If you need to run the loopback in GNU Radio - there are few hacks that are needed. This example (author of it is Martin Braun) captures all of them and it works with recent UHD:\ https://github.com/gnuradio/gnuradio/blob/main/gr-uhd/examples/grc/rfnoc_radio_loopback.grc I’m using

[USRP-users] Triggering of Rx synchronously with Tx in RFNoC

2024-10-01 Thread perper
Hello all, I know the topic of triggering of transmission and reception has been recurring here on the list over and over. But I haven’t found the answer that is good for my case among the previous threads . The context: I'm using USRP X410 and I’m transmitting a pulsed radar waveform. I’m abl