Usually, I generate signals by MATLAB and convert it to binary data. Then, I
use “rfnoc_replay_samples_from_file” utility like the following:
./rfnoc_replay_samples_from_file --args
‘type=x300,addr=192.168.20.2,second_addr=192.168.40.2,master_clock_rate=200e6,ignore-cal-file=1’
--freq 2.3e9 --f
On 27/08/2024 12:04, Brajesh wrote:
After building setup for N210R4, I am able to generate new image for
N210R4. I want to burn newly generated image on the N210R4 FPGA.
Looking for command to do the needful.
Thanks and regards.
___
USRP-users maili
After building setup for N210R4, I am able to generate new image for
N210R4. I want to burn newly generated image on the N210R4 FPGA. Looking
for command to do the needful.
Thanks and regards.
___
USRP-users mailing list -- usrp-users@lists.ettus.com
To
On 27/08/2024 09:24, Hossein via USRP-users wrote:
Yes, there are 6 calibration files (.cal) under ~/.local/share/uhd/cal
for both daughterboards (tx_dc, tx_iq, and rx_iq) with serial No. of
daughterboards in the file names.
Thanks for your interest!
So, what LO offset are you using? (You
Yes, there are 6 calibration files (.cal) under \~/.local/share/uhd/cal for
both daughterboards (tx_dc, tx_iq, and rx_iq) with serial No. of daughterboards
in the file names.
Thanks for your interest!
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On 27/08/2024 07:50, Hossein via USRP-users wrote:
I work with a USRP X310 and two CBX-120 daughterboards. I would like
to calibrate the daughterboards according to the page
https://files.ettus.com/manual/page_calibration.html on USRP Hardware
Driver (UHD) manual. After applying the utilities
I work with a USRP X310 and two CBX-120 daughterboards. I would like to
calibrate the daughterboards according to the page
https://files.ettus.com/manual/page_calibration.html on USRP Hardware Driver
(UHD) manual. After applying the utilities for self-calibration, with or
without 50 Ohm termina
Thank you for your response and for confirming the general approach to the
configuration. I have a couple more questions related to RFNoC, particularly
about buffer size in SEP (Stream Endpoints) and IP address settings.
1. Buffer Size in SEP:
I’m having some difficulty understanding the correc
On Mon, Aug 26, 2024 at 7:14 PM Olo via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Thank you for your detailed responses to my previous questions. I
> appreciate the information provided about the limitations and potential
> issues related to FFT size and TwinRX configuration.
>
> However,
If you had a polyphase channelizer on the FPGA, that would be an efficient
solution to your problem, but there's no such block as part of UHD itself.
There have been channelizer blocks written in the wild, but that would be
something you'd have to figure out.
--M
On Tue, Aug 27, 2024 at 7:17 AM O
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