Hi Marcus,
Do you know what the Pulse Width of the PPS in the N3XX GPSDO is? (I.e. how
much time difference would this result in?).
I've been seeing ~100ms of timing error with an N320 using GPS vs an N320
using WR, that I've been trying to debug. I'm using UHD 4.4 so I'm
wondering if this could
On 15/01/2024 20:05, Rob Kossler via USRP-users wrote:
Hi Eugene,
Are you expecting that the RF output (for Tx case) should be synced to
the PPS "at the RF output connector"? It is my understanding that the
sync occurs at some place in the FPGA logic for the "radio" block.
There will be delay
On 16/01/2024 12:10, Eugene Grayver wrote:
Hi,
There should be some delay, but it should be on the order of a few
clock cycles (ADC/DAC latency). For the N321 we are observing 100us,
corresponding to ~2000 samples. The X310 delay is ~1us, which
corresponds to 20 samples. Still a lot higher
Greetings,
With the UHD 4.x and the radio being a block in the RFNOC, is there a way to
write the signals input to the GPIO pins of a BasicRX daughterboard to the
Ethernet payload? I understand they can be used to control the radio, but I’d
like to see their state in an output binary stream (s
On 17/01/2024 04:57, je.amg...@gmail.com wrote:
Hi,
I am currently conducting frequency synchronization tests on two USRP
X310 devices, each equipped with different daughterboards – the first
with a UBX-40 v1 Dboard and the second with a WBX-v3 simple GDB
Dboard. In my setup, I am using an R&
Hi,\
I am currently conducting frequency synchronization tests on two USRP X310
devices, each equipped with different daughterboards – the first with a UBX-40
v1 Dboard and the second with a WBX-v3 simple GDB Dboard. In my setup, I am
using an R&S SMF 100A generator to produce a sine wave spanni
