That would be the radio reporting the overflow then. So, it sounds like
your gate causes data to back up into the radio where it eventually ran out
of room. Increasing the PYLD_FIFO_SIZE makes more space for data to buffer
up, increasing the time before an overflow would occur
Wade
On Fri, Aug 18
On 18/08/2023 12:19, jmalo...@umass.edu wrote:
Hello,
I have an application where I need my logic within the FPGA to access
the gps time. According to the spec sheet, the x410 has a gps module
built in. I would like to get gps time from it, but it is unclear
where I can get it from.
I ass
Hello,
I have an application where I need my logic within the FPGA to access the gps
time. According to the spec sheet, the x410 has a gps module built in. I would
like to get gps time from it, but it is unclear where I can get it from.
I assume the gps time is stored in radio_time inside the
On 18/08/2023 11:11, Mushtaq A. Syed, Ph.D. via USRP-users wrote:
Hi:
We are planning on using the USRP E312 SDR for a
program at Verus Research. This would require customization of the
FPGA code that will ship with the device. Since we don’t want to start
the development fro
Hi:
We are planning on using the USRP E312 SDR for a program at
Verus Research. This would require customization of the FPGA code that will
ship with the device. Since we don’t want to start the development from
scratch, we would like to know if Ettus provides source code for the
I was reading the metadata to check for a overflow (similar to the examples).
Is there a way to check specifically what block is giving an overflow? I only
know how to check if there is an overflow.
I was able to increase the overall data rate without overflow by increasing
PYLD_FIFO_SIZE of th
