My own experience is that 200 S/s on two channels is very difficult to
achieve from the host. Separate streamers may help, but you will likely
need to move to DPDK to get the best performance. I have not tried DPDK
recently, but when I tried it a few years ago, the performance was
excellent, but it
On 13/06/2023 15:17, Rob Kossler wrote:
Hi Michael,
LZ631368043US
One calibration procedure could be that you simply add a digital phase
offset to your 2nd Tx channel until your oscilloscope traces line up
to your satisfaction. It would be nice if the default FPGA image
included a
Hi Michael,
One calibration procedure could be that you simply add a digital phase
offset to your 2nd Tx channel until your oscilloscope traces line up to
your satisfaction. It would be nice if the default FPGA image included a
simple Rx & Tx complex scalar for this exact purpose (inside the DDC &
On 13/06/2023 13:50, Michael Toussaint wrote:
Hi Marcus,
Yes, the cables are identical, we also experimented with Phase stable
test cables but did not see any improvement. We understand there will
be some residual phase errors, but the RF coming out with a 2.64ns
delta or ~135 degree phase sh
On 13/06/2023 13:50, Michael Toussaint wrote:
Hi Marcus,
Yes, the cables are identical, we also experimented with Phase stable
test cables but did not see any improvement. We understand there will
be some residual phase errors, but the RF coming out with a 2.64ns
delta or ~135 degree phase sh
Hi Marcus,
Yes, the cables are identical, we also experimented with Phase stable test
cables but did not see any improvement. We understand there will be some
residual phase errors, but the RF coming out with a 2.64ns delta or ~135
degree phase shift @ 144MHz seems like more than that. Is that lev
On 12/06/2023 22:03, Aaron Smith wrote:
Hello All,
I am trying to transmit on two UBX-160 daughterboards within a single
X310 at 200 Msps using UHD 4.1.0.5-3.
I am experiencing periodic underflows, and I have already applied all
of the tips in the "USRP Host Performance Tuning Tips and Tric
Hello,
I am looking to increase my custom image from a sampling rate of 250 to 500
MS/S. I am looking to get some clarification on a few things.
Looking through the verilog, it appears both the 200 and 400 images have the
same master clock rate of 250 MHz, but with the 400 image there are twice
