Here's a quick explanation. FPGAs have clocks that control the transfer of
data between its internal registers. The Xilinx Vivado tool does a timing
check during build to make sure that the paths from each driving register
to each receiving register is not too long for the specified clock period.
W
It says the IP is locked. Perhaps you have old IP left over from a previous
build that used an older Vivado version (the Vivado version changed with
UHD 4.3). Try doing "make cleanall" to remove all the IP before building it
again. Also, do a 'git status' and make sure you don't have any extra file
I’m trying to build the x310 base image on RHEL9. I keep getting build errors,
despite the fact that I built UHD 4.2 no problem. The steps I followed:
1. Check out the v4.3.0.0 tag
2. source setupenv.sh --vivado-path=/path/to/Xilinx/Vivado/
3. make X310_XG
Did the process for building change?
Hi,
In the framework of a research project, I need to be able to use the FPGA PS to
modify the internal PPS (postpone or anticipate a single PPS pulse). I've
modified the design to manipulate the internal counter of the
n3xx_clocking/pps_gen_25 module. The latter generates the internal PPS in
