I made all design on GNU Radio. Now, I am struggling to make system more
efficient.
To decrease frequency switch time, I found IQ Imbalance mode. AD9364 is
automatically made IQ balance. If I turn off this, the switch process is
speeding up almost %30. Is there any relation with this? And I don
On 2022-07-07 05:51, STEFANI, Maurizio (External) via USRP-users wrote:
HI,
I need to program the ubx-160 via FPGA using my VHDL code.
Basically the UBX-160 is managed by a PLD but I have not the data
format and protocol to be used.
Is there someone can help me with these info about the for
On 2022-07-07 01:34, ouzan...@hotmail.com wrote:
Hello Marcus, thanks for answering.
I have different questions. Is parallel working possible? I connect
SDR to my PC. I want to SDR takes signal and meanwhile the PC makes
read, write and plot.
You might want to look into Gnu Radio, which is
Hi Stefani,
I don't think even I could find that CPLD design code. Also, I'm honestly having a very
hard time figuring out what you'd achieve by that – the CPLD really does but a tiny bit of
logic/timing glue on the UBX; what is it that you want to achieve by modifying it? Maybe
we can help yo
HI,
I need to program the ubx-160 via FPGA using my VHDL code.
Basically the UBX-160 is managed by a PLD but I have not the data format and
protocol to be used.
Is there someone can help me with these info about the format to program the
ubx?
Thank you in advance
Maurizo stefani
The informatio
