Thank you everyone for your help! I’m still not sure exactly the ratio between
the above parameters and timed command queue depth, but I empirically
determined that I now have a queue depth of 64. The other key observation was
to set rf_freq_policy to NONE, which increased the effective depth of
I am trying to trigger the acquisition of a B210 on a GPS to collect timing
signals (expected to be aligned on GPS).
Until 2020, the sequence provided by Paul Boven on this mailing list
curr_hw_time = self.uhd_usrp_source_0.get_time_last_pps()
self.uhd_usrp_source_0.set_time_next_pps( uhd.tim
Hi sp,
Simulation is the best way to debug issues like this. I suggest you modify
the provided gain testbench to test your block. That's the best way to
debug HDL code. After it's working in simulation, then you should try
running it on the FPGA.
Looking at your noc_shell_gain.v, it looks like yo
When I want to build UHD 4.2.0.0 I faced with below warning.
> IP license key 'ten_gig_eth_pcs_pma_basekr@2015.04' is enabled with a
> Design_Linking license.
Building FPGA process cannot go to compile other IP cores and stays in
ten_gig_eth_pcs_pma IP and repeats...
For UHD v4.1.0.5 I had no p
On 2022-06-16 01:03, Dominic Schaub via USRP-users wrote:
Please forgive me if this information is out there and I just happened
to miss it. I have an application where I won't have a good match
between one of the output TX ports on the USRP 2974 and the connected
load . What is the maximum per
Dear all,
I have a DPDK initiation problem
I installed DPDK19.11 with apt install and install UHD4.2 from source and in
the uhd.conf file I wrote the dpdk driver path as
dpdk-driver=/usr/lib/x86_64-linux-gnu
then I follow the instruction of Getting Started with DPDK and UHD to run the
uhd examp
I examine all of the code again and again but my problem is not solved
yet...
any RFNOC developer can not guide me?
thanks in advance
On Tue, Jun 14, 2022 at 11:21 AM sp h wrote:
> When I added ce clock domain to gain block and synthesized it, in Gnuradio
> it generates
> I attached my sou
Hello,
And so I wrote one :) Greatly inspired by the axil_ctrlport_master I mentioned
earlier of course. (I named it ctrlport_axil_master ;) )
Do you think that it would be useful to share it somewhere ? And the same goes
for the RFNoC blocks implementing LDPC encoding/decoding, would it be use
