Hi,
Thanks for the answer.
I think that what I'm trying to do should be possible since the addsub
example has an option for a hls instance. Maybe I have not explain myself
well.
I have a top level module which includes several .vhd sources alongside
with an ip from xilinx. I can instance this top
Hi, You should not expect that integrate or add Xilinx IP core directly to
RFNOC blocks, Even If you be a master in Verilog...
If you see the UHD source code you will realize that UHD is an RFNOC
framework for USRP ...
For working with the RFNOC UHD framework you should know more details:
1)Please