Is it possible that I changed center frequency and gain of USRP from the
Verilog code?
I study API CPP Gnuradio and UHD, In CPP we can change the frequency and
gain of USRP easily ...
But for me there is a question can I change the frequency or gain USRP from
Verilog in an RFNOC block?
Thanks in a
Just passing on that I updated an N320 to UHD 4.2.0.0 and ran into the TDC
error pretty quickly. I now reverted that radio to 4.1.0.2 and have not seen
that error "yet".
Thanks,
Jim
From: Jim Palladino
Sent: Monday, May 9, 2022 1:08 PM
To: Marcus D. Leech ; usr
On 2022-05-10 08:48, maxime.dup...@obspm.fr wrote:
Hi,
I followed the tutorial "Getting started with RFNoc4" for making the
demo block as suggested in the tutorial. I am working with uhd version
4.2 and a x310
I can build a FPGA image with the OOT block just fine and I get the
expected uhd
Hi,
I followed the tutorial "Getting started with RFNoc4" for making the
demo block as suggested in the tutorial. I am working with uhd version
4.2 and a x310
I can build a FPGA image with the OOT block just fine and I get the
expected uhd_usrp_probe output:
| __
I developed an RFNOC block for USRP x300, When I want to test it in
Gnuradio, the block does not work and I am faced with the below errors ...
How can solve my problem? I mention that it has a critical warning in
synthesis ...This warning is below link:
https://lists.ettus.com/empathy/thread/7HN6J
