[USRP-users] Re: Fir Filter RFNoC

Hi Camille, Sorry for the delay. I was out of town until today. I was able to take your example and make it work for me. I used the same YAML as you, except I changed firS to fir0. What UHD version are you using? You might consider updating to the latest (v4.1.0.5) and recompiling your FPGA. I tes

[USRP-users] Re: N321 LO sharing between RF 0/1

Thanks rob! > On Jan 19, 2022, at 09:41, Rob Kossler wrote: > > On Wed, Jan 19, 2022 at 1:00 AM Paul Atreides wrote: >> >> Ok, so just circling back on this. Ive got a decent handle on the Python >> API. I’ve confirmed the LO signal comes out of the port once the splitter >> output is ena

[USRP-users] Re: N321 LO sharing between RF 0/1

On Wed, Jan 19, 2022 at 1:00 AM Paul Atreides wrote: > > Ok, so just circling back on this. Ive got a decent handle on the Python API. > I’ve confirmed the LO signal comes out of the port once the splitter output > is enabled. > > Rob you’re saying that for sure both channels need to be external