On 10/22/2019 12:35 PM, Pablo Martínez de Leiva Díaz wrote:
We can't determine how much distance, from current frequency, is
enough to reproduce the error.
It seems that it also depends of which is the "first tune" frequency,
for example:
- if the first tune freq is 100Mhz, when you try
Hey Jorn,
get_max_num_samps() is "Get the max number of samples per buffer per
packet." [1]. I haven't dug into it, but I'd guess that this is something
that's dictated by your data type and your NIC's MTU. Does that return
value change when you adjust your host side MTU?
-Sam
[1] https://files.
Hey Jason,
Are you making sure that you're setting your TX time tag to be 2 seconds
ahead of the USRP's sense of time? A late packet means that the time a
packet should be executed on has already passed (as far as the USRP is
concerned).
You can use calls like:
get_time_now()
get_time_last_pps()
Well, for devices like TwinRX there are two subdevs per slot.
Sent from my iPhone
> On Oct 22, 2019, at 2:51 PM, Richard Bell wrote:
>
>
> I think I sort of figured it out, though the motherboard, subdevice and
> channel terminology is still confusing.
>
> 1) Each USRP X300 has 1 motherb
I think I sort of figured it out, though the motherboard, subdevice and
channel terminology is still confusing.
1) Each USRP X300 has 1 motherboard
2) Each motherboard has two subdevice slots, A and B
3) Each subdevice slot has 1 channel
If I want to use both subdevices on USRP1 and only one subd
Could you share your flow graph with us?
What daughtercards do you have installed?
Sent from my iPhone
> On Oct 22, 2019, at 2:16 PM, Richard Bell via USRP-users
> wrote:
>
>
> Hello,
>
> I'm a little confused about how I should distinguish between two different
> USRPs X300's and the two
Hello,
I'm a little confused about how I should distinguish between two different
USRPs X300's and the two different motherboards per USRP X300 in this type
of setup. I am feeding a 10 MHz ref and PPS ref to both USRPs. What I have
right now is a gr flowgraph with a single USRP Sink block that I h
Hi all, I have a new i9-9900K Ubuntu 18.04 machine with kernel 4.15.0.
Despite the NI PCIe driver compiled and loaded with no problems, I can't
make the X310 (over PCIe) work.
I have a similar setup with an i7, same kernel version and it works
perfectly.
Any insights or suggestions would be appreci
As I have mentioned a bit earlier, I have noticed that there was an issue
trying to run a no-Os setup but was not getting ACK from the TCA9548
expander. [Curious if anyone has gone the no-Os route and found an issue
there.]
I went ahead and proceeded to make a bin file from a HG bit file (used th
We can't determine how much distance, from current frequency, is enough
to reproduce the error.
It seems that it also depends of which is the "first tune" frequency,
for example:
- if the first tune freq is 100Mhz, when you try to change it to
500Mhz you get the error.
- but, if th
Hi all,
Can we have daughterboards TwinRX and UBX working under the same multiUSRP
object? For instance, two TwinRX attached to one USRP and two UBX attached
to another USRP creating 6 synchronized and phased aligned receiver
channels?
The discussion below stated that the sampling rate mismatch (
Hey,
I am currently setting up an E320 and want to use both TX Chains
simultaneously. I first did the benchmark_rate test:
$ ~/pybombs_gnuradio/lib/uhd/examples/benchmark_rate--args
"addr=192.168.10.2"--duration 60--channels "0,1"--rx_rate 1e6
--rx_subdev "A:0 A:1"
This ran fine
To answer myself; I found the reason shortly after sending the mail. Two days
of trial and failure :)
I set the spp value to the same as num bins, in this case 512
(stream_args->args[«spp»] = 512). When changing this value to 508 the «ghost
signal» disappeared, also with LO offset. I noticed ea
Hi,
I am running a testbench on my architecture, and all default tests pass as
expected. This includes TEST 4 which tests writing and reading back from
registers. The problem is - the following tests prove the registers hold
their initial (default) value and not the value I tried writing to them i
Hi Martin,
Thank for your answer.
1. The definition of the parameters are:
* initial begin : tb_mainstring s;logic [15:0] real_val;logic
[15:0] cplx_val;logic last;logic [31:0] random_word;logic
[63:0] readback;*
2. The error is in the readback value.
When i chec
Hi Robin and Marcus,
Thanks for your hints.
UHD 3.14.1.1 work perfectly fine with my X310s. Only the N310s seem to
have problems. I use the default HG FPGA image that ships with 3.14.1.1.
For the moment, I use `VERT2450` antennas. The ones you can order from
Ettus. I transmit/receive @2.484GHz
Hi list,
I am writing a C++ software which will scan through a given frequency range and
perform an fft. The software seems to do what it should, however something
weird happens when using LO offset tuning. With the following settings all
looks correct:
Sample rate 6.4M - master clock 51.2M -
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